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Comment by gosub100 | Hacker News Reader

Can I ask an un-related question? In a CPU with thousands of pins, how come they use N pins for ground, N pins for VCC, when it seems simpler to have continuous bar-shaped contacts? Then pins would only be necessary for signals that actually changed. I see this in computer power supplies as well, they use N separate wires to carry V+ and N more for GND, but if you need more current why not use a thicker wire and only have 2?

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> In a CPU with thousands of pins, how come they use N pins for ground, N pins for VCC, when it seems simpler to have continuous bar-shaped contacts?

I can't speak to cpus with thousands of pins, but with significantly smaller chips that often have N>1 vcc or ground, it's typically due to layout convenience. The multiple vcc may be on e.g. opposite sides of the chip, and that makes it easier to route a pure vcc signal to a spot that needs it. It's easier to route outside the chip than inside the chip, because there's more space.

Additionally, there's also a benefit to standardization. Adding different pin styles makes the part harder to design and manufacture.

This improves the impedance of high speed signal transmission - at high speeds the currents want to flow through the ground path as close to the signal path as is possible. Said another way - designers work to reduce the total area inside the electric circuit to support high switching speeds. The additional power pins in high pin count chips serve to reduce the distance between high speed signal paths and their return ground paths. This is actually true for both ground and vcc, but is easier to visualize when working with signals and their grounds.

I've never seen it on large logic chips, but this is pretty common on power ICs. Look up TI's HotRod QFNs for a particularly well-marketed example. Of course, the fab processes here are basically stone-age (for example, 0.6um BCD is still very common), so such things are easier to do and more beneficial for high-power parts.

> if you need more current why not use a thicker wire and only have 2

How do you route that current in one pin to the two locations the two pins handled? You've just moved the point where the split happens from on the motherboard to on the chip package.

you could have 2 bus bars around all 4 sides of the CPU, and tap off them at the point where the die has its connectors to the "body" (enclosure?) of the package. All the die pics I've seen, the tiny gold signal wires still route around the edges (i.e. they don't join the die in the center). So a thicker bus should work for the main voltage supply. But as the sibling commenter said, it has to do with signal impedance.

You are looking at wire bonded chips. Wire bonding is still used for chips in older process nodes and lower number of IO. This article says up to 800 IOs

https://semiengineering.com/wirebond-technology-rolls-on/

But all the high performance chips in leading edge process nodes like 3nm are flip chips. The last time I worked on a wire bond chip was in 130nm in 2004.

With a wire bond chip you can only have IO for signals and power/ground around the periphery. Some wire bond chips have 2 rings of IO pads but it makes the wire bond angles complicated. It's difficult to jump over other wire bonds to get closer to the center.

https://en.wikipedia.org/wiki/Flip_chip

Flip chips have a series of bumps above the top layer of the chip. These bumps are then connected to a small PCB inside a package or some other kind of interposer.

The transistors are on the bottom of the die and then up to 18 layers of metal are built on top. In a wire bond chip the heat has to go up through all that metal stackup which is usually encased in a glob top which isn't great for heat transfer.

https://www.gluespec.com/blog/glob-top-encapsulation

In contrast a flip chip has the die mounted upside with the top layer mounted to the PCB and the side with transistors is on top and can be directly mounted to a heat sink. Intel and AMD used to have bare die around 2000 but then mounted heat spreaders on top because sometimes people would mount the heat sink incorrectly and crack the corner of the die when tightening down non-uniformly.

http://mantravlsi.blogspot.com/2014/10/flip-chip-and-wire-bo...

With a flip chip we can have over 15,000 IO in the chip. The flip chip bumps can be all over the die not just the periphery. Not only can we put IO in the center but the density of the bumps can be much higher compared to the pad points where a wire bonder would attach.

As for your original question about some kind of continuous bar shaped contact we have a power grid underneath on every layer to distribute the power across the chip. This has to go from the top layer Metal18 down through vias to the transistors below Metal1.

Modern chips have multiple voltages in multiple voltage domains. The DDR and PCIE sections have their own voltage requirements. The standard cells that are the combination logic within a CPU operate on much lower voltages. We have dynamic voltage control where the voltage is lowered to save power. We have voltage islands where the USB port can be shut off if nothing is plugged in or CPU core 1 is active while cores 2-4 are off saving power. This requires dedicated power / ground bumps and head switches to disconnect power to sections of the chip.

I don't think we could manufacture your concept of a "bar shaped contact" because the process DRC (Design Rule Check) stuff is very rigid about what can be manufactured. Certain shapes, widths, and turns decrease the yield so they aren't allowed.

https://www.vlsi-expert.com/2014/12/design-rule-check.html

Stupid question: is “bump” the actual name for the bumps you talk about or is there some tricked out fancy name for them? (Curiosity only.)

Yes, "bump" is the actual technical name. You can click on the wikipedia link I posted to flip chip.

You can see a diagram here of the layer stack up. You can see that the solder bump on the top that connects to the outside world is huge compared to the internal metal layers.

https://en.wikipedia.org/wiki/Back_end_of_line

A standard cell in 5nm is around 200nm in height. The width can vary but this way all the cells go together like Lego bricks. Each metal layer going up from Metal1 to the top gets wider and thicker. By the time you get up to Metal18 or so it is probably 20 times wider and thicker than M1. This is useful because those upper layer metals distribute the power and ground and a chip wide clocks. The large top layer metal is also required for the huge bumps above that connect to the outside world.

I think the current minimum bump pitch is around 130 microns. You can see these with your eye and don't need a microscope. Do the math on a chip that is 25mm by 25mm and a pitch of 130 microns and you can determine how many bumps you could fit on the chip.

I wish I could give you more than just a "thank you", I love learning stuff like this, and I appreciate you explaining it in detail.

You're welcome. I'm a physical design engineer. This is what I do

https://en.wikipedia.org/wiki/Physical_design_(electronics)

This is the program I use everyday. It has a list price of over $1 million for a single license. My company has about 800 licenses but we probably get discounts of 60%

https://www.cadence.com/en_US/home/tools/digital-design-and-...

https://www.youtube.com/watch?app=desktop&v=TDvq1hVXzRc

I worked at ASML San Diego for about a year as a bottom-rank software engineer (contractor) for 7nm. The scale and complexity of the thing was mind blowing. I worked on the seed laser team, alongside the team that did the molten-tin gun. I think that domain is a rare case where the users (people like you) have a higher knowledge burden than the manufacturer. I can't imagine what actually goes on (in Taiwan and elsewhere) to actually use the machines and sign off the wafers as good-to-go.

That is really cool. I've been in the industry for over 25 years and I've never been to a fab. The number of jobs and specialization is so high that you need thousands of experts in their area but they have little knowledge about someone else's job. I know very little about all the equipment used to make chips. The people next to me that write Verilog know very little about DRC violations that I described. It takes a team of thousands of engineers to make this stuff.

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