Comment by schoen | Hacker News Reader

Comment by schoen | Hacker News Reader

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A frustrating thing is that the process node name has decoupled from the feature size:

> Later each new generation process became known as a technology node or process node, designated by the process' minimum feature size in nanometers (or historically micrometers) of the process's transistor gate length, such as the "90 nm process". However, this has not been the case since 1994, and the number of nanometers used to name process nodes (see the International Technology Roadmap for Semiconductors) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per square millimeter).

So each recent process has an explanation on Wikipedia like

> The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.

Respectively from

https://en.wikipedia.org/wiki/Semiconductor_device_fabricati...

https://en.wikipedia.org/wiki/3_nm_process

So, is 3nm not thinner/smaller in size compared to 5nm?

I think there is a bit of an exaggeration in the previous comment.

Feature sizes decoupled from process node names mid-90s somewhat mildly, with transistor density remaining accurate to the naming. With introduction of FinFET transistors (2012, Intel 22nm), feature size and node naming truly decoupled completely, but node naming still remained largely true to transistor density.

Transistor density started drifting apart from the node naming only recently, and in part it has to do with ever increasing difference in transistor density and its rate of improvement in different parts of the design, especially between logic (shrinks the fastest), SRAM (used for various caches and even register files), and IO (like DRAM controllers, shrinks the slowest).

3nm is smaller than 5nm. It's just there is quite literally not a single meaningful distance measurement in a 3nm design that measures 3nm, just like there is nothing 5nm in a 5nm design - most features are much larger than that physically. Further, (5/3)^2 ~= 2.8 may suggest that this is a 2.8x increase in transistor density, which it absolutely isn't, it's just nobody wanted to name the node 3.5 to yield more accurate and very traditional 2x ratio ((5/3.5)^2 ~= 2). Furthermore, even 2x would be misleading, only logic density increase somewhat approaches that figure:

logic: 1.7x SRAM: 1.25x IO: 1.11x

As chips contain all of these components, overall external area (physical size of the entire finished chip) of real-world chips going from 5nm to 3nm is shrinking by about 1.3-1.4x or so, far cry from (very) old school 2x, never mind 2.8x that naming may suggest.

To make things even more complicated, the following is also true: long time ago the cost of the chip was practically proportional to its area almost regardless of the process node used, therefore, 2x smaller chip costed almost 2x less to produce. Not anymore. Now every new node is substantially more expensive per unit area to use, thus a smaller chip on a newer node ends up costing only marginally less - and in some instances, more - than a bigger (by area) chip on an older node.

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