For those not in embedded: the SO (not S0) pin is commonly called MISO (Master In Slave Out) in a SPI bus; it is the pin on which the SPI device (SPI flash) sends data to the controller (ethernet bridge). The CS (Chip Select) pin of the device, on the other hand, is supposed to be held at logic low during an entire SPI transaction. Tying a pin that should transition between high and low to a pin that should stay low would likely screw up the communication and make the ethernet bridge think a SPI flash is not there.

I thought the art of making wildly inconvenient UX assumptions on behalf of users had largely stayed in software, eg. websites doing “copied to clipboard!” completely unprovoked overwriting whatever you have kept in system clipboard. A few years ago I had a Realtek wifi adapter that would sometimes do this too on Windows though at least it didn’t try to hide the network device. It’s hilarious that this design trend has even found its way into silicon, though I suspect it’s rarer these days now.