It seems the author started with a notional combinational subcircuit presumably operating in a single clock domain, then summarily unloaded a foot shotgun by deciding an initial behavioral fix was to infer a flip flop clocked by an input signal.

At face value, this:

  always @(posedge RDMGI, posedge RINIT, posedge cycle_finished) begin
  ...
  assign TDMGO = RDMGI & ~won_arbitration;

...was just asking for metastability in that it transformed the subcircuit into a clock domain crossing problem. Recognizing this, it makes sense that the sol'n[1] was to dual flop synchronize the async RDMGI input.

[1] http://www.froghouse.org/~dab/papers/bus-arbitration/grant4....