On Bus Arbitration on the Unibus and QBUS (2017) | Hacker News Reader

On Bus Arbitration on the Unibus and QBUS (2017)

froghouse.org

40 pointsuserbinator7 comments

It seems the author started with a notional combinational subcircuit presumably operating in a single clock domain, then summarily unloaded a foot shotgun by deciding an initial behavioral fix was to infer a flip flop clocked by an input signal.

At face value, this:

  always @(posedge RDMGI, posedge RINIT, posedge cycle_finished) begin
  ...
  assign TDMGO = RDMGI & ~won_arbitration;

...was just asking for metastability in that it transformed the subcircuit into a clock domain crossing problem. Recognizing this, it makes sense that the sol'n[1] was to dual flop synchronize the async RDMGI input.

[1] http://www.froghouse.org/~dab/papers/bus-arbitration/grant4....

Correct me if I'm wrong about this, but according to one of the author's cited references, the time needed for metastability to resolve is theoretically unbounded. Why wouldn't every solution based on introducing a fixed delay amount to kicking the can down the road?

Because the resolution is theoretically unbounded but decays exponentially if you don't do something stupid.

Two flip-flops in series is almost always enough to resolve the uncertainty.

However, I'm extremely skeptical of all the "metastability" fixes applied here. You only care about synchronizers when you change between unrelated clock domains.

Yes, the PDP-11 is before the advent of widespread knowledge about metastability. However, open-collector busses were not unusual at the time. Glitches were also understood. You set your logic transitions to cross boxes of your Karnaugh map correctly to avoid them. None of the given circuits seem to fix that at first glance, but I'd need to look at it in more detail.

I suspect the issue is that he is using flops instead of latches. Latches are level sensitive while flops are edge sensitive.

A lot of open-collector arbitration is more of something gets yanked down, you see something got yanked down so you also yank something down (this need to happen fast and is in hardware), then you release something if you don't have anything to say (this can happen slowly in software since you already yanked things and locked it), after everybody but one releases the bus arbitration is over and the winner can now proceed to use the bus.

I understand it to be a matter of pragmatism over formalism, i.e. given an appropriate system, if you could probabilistically kick the can so far down the road that the chances of system failure become overwhelmingly dominated by factors other than metastability, is it still a real problem?

I ask with an inpert mindset recognizing who you are.

If you’re interested in this topic, Computer Engineering: A DEC View of Hardware Systems Design is a must-read:

http://bitsavers.org/pdf/dec/_Books/Bell-ComputerEngineering...

Interesting that people are doing this in 2017. I wonder why.

Disclosure: I have a couple cupboards full of Unibus and QBUS boards.

Some of us have working systems (a 11/23+ and an 11/730). The biggest problem with all of them is the disk drives are 30-50+ years old and dying. So there's a reasonable amount of activity around building new controller boards talking to more modern/reliable mass storage.

And if you want to clear out that cupboard, do let me know. :-)

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