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> T1 is dead slow on floating point, the situation is so horrible to the extent that it is just a fraud, period. I mean why would anyone with a reasonable mind expect their fancy 5 figures purchase to be so slow on floating point?

It was designed for the heavily parallel web workloads of the 2000s, which don't use floating point, hence the multiple threads per FPU.

> It was designed for the heavily parallel web workloads of the 2000s

No. According to its official datasheet, "this processor targets commercial applications such as application servers and database servers".

I thought floating point is an essential part of databases.

That being said, given it is a fraud from the beginning, I can accept the fact that the official T1 datasheet is intentionally misleading its potential buyers.

> which don't use floating point, hence the multiple threads per FPU.

are you implying that it was mistake to implement more FPUs in their subsequent T2?

there are certain shortcuts you don't make in engineering. when building an generic processor aiming to take on the application & database servers, you don't stupidly have a single FPU for the entire processor when letting your big mouth PR department talking about how great is the throughput.

> I thought floating point is an essential part of databases.

Have you ever implemented a database? Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data.

That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses.

It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments.

> Have you ever implemented a database?

Yes, multiple times, in both American companies and in Chinese startups.

> Most operations (filtering, joining, indexing) are purely integer workloads with large working sets that are likely to stall the processor while waiting for data.

That is not a justification for having only one FPU. Let's use logic here, it is not that hard.

> That's exactly the scenario that was targeted with that processor design, many threads per core such that the cores are always busy even if some of the threads are stalled on memory accesses.

Again, that doesn't justify the stupidity of having just one FPU.

> It wasn't meant for single threaded workloads or HPC workloads, and afaik wasn't marketed for those segments.

I am now totally confused. You are defending the stupid T1 design which only has 1 FPU for its entire processor capable of running 32 threads in parallel, yet your argument is that such design is meant for multi-threaded workloads? I thought you need multiple FPUs to truly parallelize those multi-threaded workloads.

As jfim wrote (emphasis mine): "It was designed for the heavily parallel web workloads of the 2000s". At this time, this mostly meant integer workload. For todays's workloads even in this particular domain, having only one FPU for 32 threads is likely a bad idea, but at that time, this was a perfectly acceptable compromise for this kind of application. These were simply different times.

> I thought floating point is an essential part of databases.

It's not. It's not even particularly necessary for 95% of DB Ops. I have no idea where you even gathered that thought.

This drastically misinformed aspect just makes the rest of your argument seem equally misinformed.

> It's not even particularly necessary for 95% of DB Ops.

Let's say I have databases full of some sensor data that need to be processed by some fancy SQL scripts to crunch those numbers. Tell me how I am suppose to get that done without using floating point.

With only one FPU in mind, tell me how to parallelize such processing and full utilize all those cores.

Picking an example from the remaining 5% does not contradict the parent's point.

The point here is that it is pure stupidity on display to cut the number of FPUs to just one, the short lived history of such design is a proof for that.

> thought floating point is an essential part of databases

To add to the other replies to this, the number of areas where CPU floating point performance matters is shrinking. GPUs are where it's at nowadays. Also, T1 was never going to be a gaming machine or a supercomputer node. Whoever thought otherwise didn't read the actual specs, which were very clear back then.

> I thought floating point is an essential part of databases.

Good heavens, no. Why on earth would you even think that, have you any experience with databases?

> because it is a design that belong to yesterday

Which parts of the POWER architecture design belong to yesterday? Specific examples would be great.

the so called POWER architecture covers like 35 years of development, the latest iteration probably implements some of the latest stuff in the area as it is an experimental platform for researchers.

it is still a design of yesterday because you don't get access to tier 1 software ecosystem. it is a modernized VAX for hobbyists.

Still no specific examples, just handwaving?

SPARC, Intel i960, AMD29k, ARM, RISC-V and many others are direct descendants of the Berkeley RISC design.

Using the number of years of a measure of technological relevance, it can be argued that ARM and RISC-V designs are even older than 35 years. It is pure sophism, though, and it does not help.

By the same token, all modern computing architectures are fossilised designs because they are based on the von Neumann architecture from 1945.

Just want to say thank you. I could have typed that out and didn't. ( See my reply below )

My faith on HN discussions continues to fall. There are many topics I keep thinking may be I shouldn't even click on. But it is good to know there are people, who continue to contribute in a positive manner. ( at least more positive than I am )

> Using the number of years of a measure of technological relevance, it can be argued that ARM and RISC-V designs are even older than 35 years.

I don't know what you are talking about.

X86/ARM are highly successful, being 30-40 years old proves that they are well maintained & comes with a long history of good ecosystems. RISC-V is obviously rising with no limit for its future.

POWER lost the competition, it is done, it should be depreciated. With that in mind, its 35 years history is not a fancy record, it is proof that not many people are going to pick that junk up again.

x86 and ARM are well maintained because they're 30-40 years old, but Power (it's not an acronym anymore) is not because it's 35 years old?

I also suspect you're making the typical mistake of confusing PowerPC with modern Power ISA. They overlap strongly and PowerPC was virtually designed to be 64-bit ready from the very beginning, but chips based on the modern ISA are much more sophisticated.

As someone who actually works on ppc64, the biggest two things that bother me about the ISA are the weirdness with r0 and the large number of instructions that must be implemented to be practical on a new design. Those are comparable to the quirks of any other "successful" ISA by your standards. They hardly make it junk.

> x86 and ARM are well maintained because they're 30-40 years old, but Power (it's not an acronym anymore) is not because it's 35 years old?

I don't know how/why you came up with such strange idea.

x86 and ARM are 30-40 years old, with their widespread market share, such long history became an advantage as numerous tools & apps got built in that 30-40 years timeframe. it is called the ecosystem.

POWER as a failed ISA has been on its dead man walking stage for 30-40 years, nothing really get promoted & adopted. when you look back, it provides very strong certainty that if something good didn't happen in the last 30 years then there won't be a good chance for it happen in the next 5-10 years. its 30-40 years history is a disadvantage, because it is potential has been proven to be pretty bad.

This is like being 50 years old & highly successful in tech putting you in a comfort spot as your age implies your decades long valuable & successful experience. Being 50 years old with a shitty CV full of failures is a different story, your age is a huge liability for obvious reasons.

If the above is not obvious and you are in tech, then I have to say that you are in the wrong business.

What? So what is your definition of Modern architecture ? I am assuming you are referring to ISA here.

AMD64, ARM64, RISC-V.

This is not rocket science. No one needs POWER. Museum is a better place for those kind of vintage stuff.

>AMD64, ARM64, RISC-V. This is not rocket science.

You should re-read what you wrote. [1], and I will leave that as it is. And contrary to what you have been finger pointing. And no one is getting emotional.

[1]. the so called POWER architecture covers like 35 years of development,

> Which parts of the POWER architecture design belong to yesterday? Specific examples would be great.

Is this a troll post? How about the fact that POWER9 is nearly 7 years old and was more than a generation behind it's competitors at the time it launched?

Is this a troll answer?

I don't see any specific example of what exactly is bad about it in this reply, so, the question remains open.

If the answer would be so obvious that the question must be a disingenuous troll question, then surely it must be effortless to give a meaningful answer. It's a terrible architecture because it...what? What obviously backwards and never can and never could possibly work idea does it try to implement?

Not even my question but I just found criticizing the question with this answer pretty rich.

Can't imagine resorting to being this snarky in the defense of a flawed CPU micro architecture. It takes 30 seconds with a search engine to find benchmarks: https://www.phoronix.com/review/power9-epyc-xeon/3

It is, quite literally, half as performant as it's contemporaries while drawing more power. Beyond being 'open', these CPUs are duds and wastes of sand.

I can't be defending something I don't know or care about. The purpose of the comment was stated plainly.

They are just emotional.

Certain vintage tech/gears are being linked to those good old days when certain techs (e.g. SMP and Unix) were only available to selected few. The reality is clear here, we are talking about a totally failed ISA that has no economic future whatsoever.

Emotional? Hardly. I am not affiliated with POWER and have never been. But I like good hardware, good design ideas and debating them.

One could pin me on maybe getting touchy in relation to my own pet ISA design that is a unholy matrimony of an 128-bit extension of the original PDP-11 architecture, ideas from i860, AMD29k and NEC SH-4 that I have been toying around and chugging along with, running on a FPGA at home as well as running a NetBSD port on it – for fun and as an outlet when I get frustrated with the enterprise-y world where I work. But it is my own _pet_ project where I have unbashed freedom to try anything out however silly or impractical the idea is, and where I can't expect others to agree with the ideas I am entertaining.

We could have been debating the merits of the POWER vs ARM CHERI tagged memory architectures and their implications on the compiler design. Or, we could have been disagreeing on the merits of the POWER CPU assisted translation of the ISA's for z/Series IBM mainframes (with the physical CPU long, long not being in existence and POWER CPU's emulating the ISA instead) and AS/400 (or whatever it is named today – the ISA that has never been implemented in the hardware anyway and has always been virtual and powered by POWER CPU's) vs alternatives, in hardware or in software.

We could have also been locking horns over the original Cray vector instructions vs the RISC-V vector extension designs. Or, how 96x slices in a 24x core POWER CPU stack up against competing 96 core CPU designs. Or, agree and disagree how advances in the modern compiler design could have made VLIW architectures more practical today and not. Or something else.

But this:

> […] X86/ARM are highly successful, being 30-40 years old proves that they are well maintained […]

> […] POWER lost the competition, it is done, it should be depreciated. With that in mind, its 35 years history is not a fancy record, it is proof that not many people are going to pick that junk up again […]

is not worth responding to. Such comments belong in Slashdot, Reddit and similar internet forums.

We like picking things apart on here, so please allow us to endulge in it.

>Such comments belong in Slashdot, Reddit and similar internet forums.

Before 2014, most internet reporters, even if they knew HN, they wont name it. Or at best "an orange website". It is as if an accepted culture or a norm for not linking to it. To prevent the site from becoming reddit or slashdot. Somewhere along the line everyone started naming / linking to it.

That is why when ever people ask where to look for high quality information or discussion, I hesitate to even name the few site I bookmarked. Where you would find not only hard core enthusiast but also professional or industry veteran offering their informed opinion.

> AS/400 (or whatever it is named today – the ISA that has never been implemented in the hardware anyway and has always been virtual and powered by POWER CPUs

To nitpick, the original AS/400 systems used a proprietary CPU called IMPI (Internal MicroProgrammed Interface), descended from the System/38. It was ported to the POWER series, or rather the RS64 in the early 90s.

The higher-level software, including parts of the OS, and all applications target a virtual machine.

> because people don't want closed architectures owned by closed companies run by a group of morons from the PR & sales departments?

How would ARM and x86 be "open"?

The T2 fixed what you are complaining about. Was released in 2007.

The same year when SUN decided to use processors from both AMD and Intel to replace its own.

Seeing as they kept making SPARC CPUs for a decade longer, not really.

'Show me on the 1U chassis where the bad CPU touched you' is the vibe I'm getting from your comments in this thread.

> Seeing as they kept making SPARC CPUs for a decade longer

because there were poor customers stuck in the SPARC trap. it would them huge to move to a different ISA and there is usually no $ return for doing that. trying not to further damage its PR, they thus decided to keep the production going.

same logic for Intel making Itanium all the way until 2018 or 2019.