Thanks. I'm trying to think of cases where (assuming no use of the AI stuff) this actually ends up cheaper/smaller than just embedding 16x a tile's compute cores (or a smaller number of much higher performance cores) and 16x a tile's FPGA fabric... with such a small number of options and small number of tiles, I'd suspect (but could easily be wrong) that the area overhead for bonding is on the same order of magnitude as the actual logic here. And while having a large number of fast cores scattered through FPGA fabric would be /relatively/ novel, it seems like it would support the type of flexible configurability that's needed here. I could imagine that this grows in power with a growing ecosystem of tiles, but I'm stretching my mind here for tiles that actually need to be ASICs instead of just implemented in fabric.