Hmm. If this memory is faster than DRAM, wouldn't it be quick to test, say, ten trillion write/erase cycles?
Why stop at 10M? Is the erase operation really slow?
Why stop at 10M? Is the erase operation really slow?
Ten trillion cycles would take over 150 years.
I'm guessing a silicon lab doesn't have "the rest of the computer" that would allow them to run this ram at full speed constantly. This UltraRAM isn't something they can just slot into their motherboard.
10 million is 14 hours. It takes longer than that to prepare your documentation. Something is rotten in Denmark. A skeptic could very, very reasonably assume that cherry-picking is going on here, and that 10m to degradation isn't far off from the truth.
> Assuming ideal capacitive scaling[33] down to state-of-the-art feature sizes, the switching performance would be faster than DRAM, although testing on smaller feature size devices is required to confirm this.
So, they have no idea of its performance. Yet.