I pretty much only work with Xilinx/AMD parts these days, and, at least on US/US+, they do indeed all have a CE on all the flops (unless there are undocumented degenerate cells with missing features).
Note that people talk about Verilog or VHDL as "RTL languages". That is not correct - these languages allow hardware designs using any style to be modeled. But sticking with RTL is strongly encouraged. A design that uses the output from one part of a circuit as a clock to another part, for example, is not RTL. This might cause problems when moving from one FPGA to another or to an ASIC.