There is a design style called RTL (register transfer level) which works better with registers that have separate clock and enable inputs. The clock goes to all registers, but on any given cycle only a subset of those are enabled depending on the current state. Since these enables are generated from the outputs of these registers which then pass through some combinational logic, they will be stable around the rising edge of the clock.

Note that people talk about Verilog or VHDL as "RTL languages". That is not correct - these languages allow hardware designs using any style to be modeled. But sticking with RTL is strongly encouraged. A design that uses the output from one part of a circuit as a clock to another part, for example, is not RTL. This might cause problems when moving from one FPGA to another or to an ASIC.