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Comment by denotational | Hacker News Reader

> However, the enable input is a fairly obscure feature for a flip-flop component; most flip-flop chips have a clock input, but not an enable.

The clock-enable is actually really common for flops in an integrated circuit; it might have been unusual in the days of discrete TTL, but as the article concedes, practically every cell library or FPGA fabric you can find will have it.

Not only is it commonly present, but the CE is used all the time by the synthesis/technology-mapping process, indeed any time you write an `if` without an `else` within a clock-edge sensitive process, the tool is probably going to use a CE.

On an FPGA, the only other option is a LUT-based feedback mux which can be undesirable for various reasons, including the use of additional routing resources if the fabric has no dedicated route in each CLB from the output flop to the input LUT, and the increased fanout on the flop.

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There were a few TTL ones available: 74x378 is one I used back in the day. It was easier to meet timing with parts like this. I used it for my PCI cards: it was part of a circuit that latched the address of PCI configuration writes- the only data that would make it to the board if the transaction times out. Why did I need this? To load the bits into Xilinx 4010E FPGA which held the full PCI interface, thereby avoiding the need for a Xilinx configuration PROM. After the design was loaded, the PCI interface would come alive and start responding to transactions.

This worked until Intel decided to save power by disabling the PCI clock on unused sockets: it means your device had better exist on the bus before the BIOS's PCI enumeration (actually this is not true- with the full bridge documentation I could enable the clock- but I didn't have it, and in any case, then the design would be chipset dependent).

Xilinx/amd fpga have a CE pin on many of its flops (if not all?). Not sure for altera/intel but would be surprised they wouldn't have.

I pretty much only work with Xilinx/AMD parts these days, and, at least on US/US+, they do indeed all have a CE on all the flops (unless there are undocumented degenerate cells with missing features).

There is a design style called RTL (register transfer level) which works better with registers that have separate clock and enable inputs. The clock goes to all registers, but on any given cycle only a subset of those are enabled depending on the current state. Since these enables are generated from the outputs of these registers which then pass through some combinational logic, they will be stable around the rising edge of the clock.

Note that people talk about Verilog or VHDL as "RTL languages". That is not correct - these languages allow hardware designs using any style to be modeled. But sticking with RTL is strongly encouraged. A design that uses the output from one part of a circuit as a clock to another part, for example, is not RTL. This might cause problems when moving from one FPGA to another or to an ASIC.

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