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Comment by thunderbird120 | Hacker News Reader

Will be interested to see how this first(ish) gen of Intel's disaggregated chips pan out. I've been needing to replace my laptop and these seem like they have the potential to be extremely nice for a mid range machine with long battery life. The new scheduler hierarchy is especially interesting given how much of the physical chip they can avoid powering on at all for most simple tasks. For a lot of light use cases the entire "real" CPU and GPU parts of the silicon can be completely dark since the SOC has two tiny cores to run things and other necessary parts things like the video decode silicon were separated from the GPU.

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Eh, I have a sneaking suspicion the compute dies won't be shut down as much as you'd think, and that there will be some extra power usage from crossing the dies like desktop Ryzen parts (though hopefully not nearly as severe).

A good Process Lasso config is probably worth the time investment. Instead of "trusting" the scheduler, you could force everything non time sensitive onto the efficiency island, maybe by default.

The 3D Foveros packaging technology is critical as it allows some path lengths to be much shorter than if you had to traverse that same path but only in the horizontal 2D plane.

Very excited to see how this plays out in practice.

I thought Meteor Lake was tiled and 2D? Intel has EMIB and such for very good bridges, but they are still bridges.

If it is 3D stacked with TSVs, thats a whole other can of worms. AMD's X3D on Ryzen 7000 creates heat/clockspeed issues, and they reportedly canceled a 3D variant of the 7900 GPUs due to similar issues.

Disaggregation is also good for risk management of attack surfaces.

> Intel has broken out the Silicon Security Engine from its traditional Converged Security and Manageability Engine (CSME).

Good to see Security separated from ME.

Hopefully the ME no longer has control over IOMMU isolation of devices.

I'm not sure I follow. It's almost guaranteed that all chiplets are still on some global system bus just like they were on their monolithic dies. Unless Intel has taken sudden great strides with their SoC security architecture, there are likely still all the old problems (plus a bunch of new fun ones!). Taking it off die is a response to the physical scaling issue, it's really not meant as a security enhancement.

Per the article, both IP blocks remain within the same SOC chiplet/tile.

https://en.wikipedia.org/wiki/Intel_Management_Engine

> Starting with ME 11, it is based on the Intel Quark x86-based 32-bit CPU and runs the MINIX 3 operating system.

If "Silicon Security" functions are now executing on a separate CPU/OS, it's an increase in separation from Intel ME functions.

https://www.anandtech.com/show/20046/intel-unveils-meteor-la...

> [Meteor Lake] introduces the Intel Silicon Security Engine (ISSE), a dedicated component focused solely on securing things at a silicon level ... The Converged Security and Manageability Engine (CSME) has also been partitioned to further enhance platform security.

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