Intel Meteor Lake Architecture
hothardware.com
hothardware.com
A good Process Lasso config is probably worth the time investment. Instead of "trusting" the scheduler, you could force everything non time sensitive onto the efficiency island, maybe by default.
Very excited to see how this plays out in practice.
If it is 3D stacked with TSVs, thats a whole other can of worms. AMD's X3D on Ryzen 7000 creates heat/clockspeed issues, and they reportedly canceled a 3D variant of the 7900 GPUs due to similar issues.
> Intel has broken out the Silicon Security Engine from its traditional Converged Security and Manageability Engine (CSME).
Good to see Security separated from ME.
Hopefully the ME no longer has control over IOMMU isolation of devices.
https://en.wikipedia.org/wiki/Intel_Management_Engine
> Starting with ME 11, it is based on the Intel Quark x86-based 32-bit CPU and runs the MINIX 3 operating system.
If "Silicon Security" functions are now executing on a separate CPU/OS, it's an increase in separation from Intel ME functions.
https://www.anandtech.com/show/20046/intel-unveils-meteor-la...
> [Meteor Lake] introduces the Intel Silicon Security Engine (ISSE), a dedicated component focused solely on securing things at a silicon level ... The Converged Security and Manageability Engine (CSME) has also been partitioned to further enhance platform security.
Does "Sensing" refer to human presence based on camera and radio (Wi-Fi, UWB) imaging?
https://lkml.org/lkml/2023/2/12/314
Intel Visual Sensing Controller (IVSC), codenamed "Clover Falls", is a companion chip designed to provide secure and low power vision capability to IA platforms. The primary use case of IVSC is to bring in context awareness. IVSC interfaces directly with the platform main camera sensor via a CSI-2 link and processes the image data with the embedded AI engine. The detected events are sent over I2C to ISH (Intel Sensor Hub) for additional data fusion from multiple sensors.
The company didn't detail how it goes about this, but technologies already exist to combine visual input from the PC's cameras; radio from the PC's antennas, audio from its mic array; to form a picture of its surroundings.
With an initial focus on respiration detection, we hope to extend the technology to detect other physical activities as well. Intel Labs will demonstrate an early prototype of breathing detection ... The solution detects the rhythmic change in CSI due to chest movement during breathing ... The respiration rates gathered by this technology could play an important role in stress detection and other wellness applications.Also how good will the p-cores be compared to previous gen?
Are the avx-10 instructions going into this generation?
Nope. In fact, it probably won't be in client until after Lunar Lake (2025+).
It is likely that Panther Lake, to be launched in 2025, probably in the second half of the year, will be the first Intel CPU supporting the 256-bit subset of the AVX10.2 ISA version.
The 2024 Granite Rapids will probably be the only Intel CPU supporting the AVX10.1 ISA version (with full 512-bit support), because all the following will start from AVX10.2.
Client support depends on E-cores supporting it, and Intel have specified that they'll start with AVX10.2. I don't believe that any core has been announced with AVX10.2 support yet, and we the latest we know is Lunar Lake's ISA support.
Granite Rapids has a few extra AVX-512 instructions (including those added by Tiger Lake, but omitted in Sapphire Rapids and Alder Lake), so Sapphire Rapids does not support all of AVX10.1. Therefore neither Sapphire Rapids nor Emerald Rapids may turn on the AVX10 CPUID bits.
Nevertheless, the differences between the AVX-512 instruction sets of Granite Rapids and Sapphire Rapids are small and of little importance.
I couldn't find any new AVX* instructions added to Granite Rapids (I see PREFETCHI and some AMX additions, neither of which fall under the AVX category), and VP2INTERSECT isn't listed under AVX10 or Granite Rapids.
What do you mean “how they let Apple do it”. Do you think Intel & AMD could stop them?
https://www.reddit.com/r/castles/comments/4t5w0q/round_vs_sq...
PCs have been stuck to 3/4Ghz for more than 15 years, so it is not like they didn't have the time to optimize from the consumption/heat point of view.
For a while Intel's process knowledge was supposed to be better, even if the design was less efficient, but that turned out to be a mirage around 10nm or so. Intel now without a process advantage is probably never going to regain it's monopoly, and so far hasn't really transformed itself to do anything other than build those high-margin chips.
Once upon a time, I wanted to use one of the chips from a company they bought in networking, but Intel's model is to make the chip and let other companies make a product to take it to market. Intel doesn't want to make a market, just sell into it. You can see that with their attempt at TV where they stopped when they didn't want to spend money on content. So the chip I was interested in didn't get much R&D or a product and it more or less disappeared, another wasted investment.
1. Arm is generally more efficient than x86. 2. Apple uses TSMC's latest nodes before anyone else. 3. Apple doesn't chase peak performance like AMD and Intel. CPU speed and power consumption is not linear. Intel has been chasing 5GHZ+ speeds the last few years which consumes considerably more power. Apple keeps their CPUs under 3.5GHZ.
This is not entirely true in general sense. Yes, a typical ARM CPU is more energy efficient indeed, but theoretically nothing prevents x86 to be nearly as efficient.
The main reason why Apple silicon is more efficient is that Apple silicon is a mobile chip basically, and competition on mobile is harsh, so all the producers had to optimize their chips a lot for energy efficiency.
On the other hand until apple silicon and recent AMD ascension there was a monopoly of Intel on a laptop market with no incentive to do something. Just look at how fast Intel developed asymmetric Arm-like P/N-core architecture right after Apple Silicon emerged. Let's hope this new competitor will force more energy efficient x86 chips to be produced by intel and amd eventually.
The very complex instruction set does. You can easily throw multiple decoders at Arm code, but x86 scales badly due to the variable length. Current cores need predecoders to find instruction boundaries which is just not needed with fixed width instructions and even then can only decode simpler instructions with the higher numbered decoders.
i.e., PSPACE ⊆ EXPTIME
https://en.wikipedia.org/wiki/EXPTIME
which is funny because people are always like "uh why do i need to understand asymptotics when machines are so fast". well the answer is the asymptotics catch up to you when the speed of light isn't infinite or when you're timing things down to the nanosecond.
The question is, how much overhead does it cause compared to the whole picture. There are empirical evidences the answer is "very little":
https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-...
> With the op cache disabled via an undocumented MSR, we found that Zen 2’s fetch and decode path consumes around 4-10% more core power, or 0.5-6% more package power than the op cache path. In practice, the decoders will consume an even lower fraction of core or package power.
Intel and AMD also make low-power parts.
You can't compare a chip running at 3ghz with one running at 5ghz. It just doesn'tell you anything useful about the architecture, only what the company configuring the chip thought mattered.
Being "only" 30% faster but using twice the power at 5ghz, for example, is entirely expected. Chances are the M1 couldnt even run that fast, or it would end up using just as much power if it did.
* Within up to 15% at 25W.
Maybe in light threads that utilize many cores.
Most reviewers base it on Cinebench which is a poor indication of CPU performance for anything except Cinemark. Cinebench uses Intel Embree Engine which is hand optimized for x86. In addition, Cinebench favors CPUs with many slow cores - which is not how most software will perform. This is why AMD heavily marketed Cinebench for Zen1 launch and why Intel heavily markets it now for Alder Lake/Raptor Lake. In fact, Intel's little cores are basically designed to win at Cinebench.
Furthermore, AMD CPUs will rate at 25w but can easily boost up to 40w+ watts. It's up to the laptop maker.
Not sure what you mean by many slow cores, since mobile zen 4 has a better single-core performance than m2 pro.
Zen4 mobile does not have higher ST performance than M2 series.
https://browser.geekbench.com/processors/amd-ryzen-7-pro-784...
https://browser.geekbench.com/macs/mac-mini-2023-12c-cpu
7840u's ST is slower by 21% while consuming much more power during the test.
But your list of Intel codenames is fantastic. It’s a great resource. Lots of beautiful names in there. Still, I wonder why they haven’t gone with crater lake such a beautiful lake and right in their wheelhouse in terms of geography.
isn't "Tile" is basically chiplet? why not just call it chiplet?
It's probably a lawyer thing like uncertainty over who owns the noun 'chiplet'.
Can't wait for Microsoft and Intel to team together to make an ultra AI search bar that can finally find files properly like back in Windows 7...
Searching for setting screens is also a pain in the ass, especially if you use different language. MS recognizes only their own translation, not the most intuitive text, not English text ... you just have to know
Or you could use literally any other search program that works wonderfully, without the indexing process using an eyebrow raising amount of CPU? Including Microsoft's own shockingly fast file search in VSCode.
> feature rich version of Ryzen's IO die
The interconnect Intel is using is more expensive/sophisticated than AMD's (but less expensive than the TSVs for the X3D chips), so hopefully its pretty good in laptops?
AMD's IO die setup burns tons of idle power, which is why the laptop parts are still monolithic.
Fortunately there's a truly excellent third-party utility that is probably the second thing I install on any new Windows install (after Chrome): https://www.voidtools.com/support/everything/
Look at how WinGet was launched with just enough effort to kill AppGet. It was a big announcement that was the equivalent of “avoid this space or we’ll crush you” and then what? Nothing innovative has happened since they killed the innovator (AppGet).
My desktop now has 24 cores (8P/16E) and now is the right time to rethink the OS.
Microsoft is definitely doing this, but they're putting all the effort into making it into an attention-stealing ad delivery platform.
For me it just there to make sure my PC boots - get's regular patches for security issues and not corrupt my file storage and play sound/videos.
The bulk of time is spent inside a JetBrains IDE/Visual Studio Code/Chrome - my interaction with the OS is just launching programs and hitting the shutdown button and Windows 11 is just great at that.
For a work OS, I want sane OOTB defaults, or a "disable all of this" option in the initial setup. These settings should be respected and not overridden in an update.
I could carry nothing forward from my old PC.
It's not built in, but it exists:
I don’t think that quality is ever coming back. No matter what, they’re going to be connecting to bing for the top results / ads, so you’ll always have a bunch of latency and will never get back to Win 7 levels of local only performance.
It’s sad and the AI, which is mostly useless based on my experience, is going to suck up even more CPU cycles and add even more latency.
For me, it takes 5 seconds for the start search to respond on first use. My 12th gen i5 with NVMe storage and Win 11 literally runs worse than my 4th gen i7 with a first gen SSD and Win 7.
Microsoft has usurped a decade of computing gains and spent them on ads and tracking. Don’t expect anything that benefits the user in the near future.
Finding a local file with an already known name is nigh-impossible with the current Windows search.
Yeah, they need to move to rivers now...
I'm more partial to the FPGAs. Sundance Mesa is a cool codename.
Therefore this is no longer a speculation.
It can be assumed that these are the first CPUs that will implement the 256-bit subset of the AVX10.2 ISA, finally extending the coverage of AVX-512 to all Intel products, but with the restriction to 256-bit registers and operations.
Panther Lake will be preceded by Lunar Lake for low-power mobile devices, either in late 2024 or in early 2025.
Before that, there will be Arrow Lake S for desktops and Arrow Lake for laptops. Despite the single name, these 2 implement different instruction sets and they will be made with different manufacturing processes, Intel 20A for Arrow Lake and an undisclosed process for Arrow Lake S (which might be made at TSMC, according to rumors, because it needs bigger tiles than what would be possible in Intel 20A).
While Meteor Lake seems to be just a shrink of Raptor Lake, which will have a much better performance only due to the greater energy efficiency provided by the Intel 4 process and due to the much better GPU made at TSMC, Arrow Lake is expected to introduce a new improved CPU microarchitecture, which is supposed to compete successfully with Zen 5.
Also the SOC with built-in AI engine. Oh boy, I wonder how long it will take for AI-assisted malware, or botnets to emerge. Exciting times!
They are using off the shelf cores that have to be good in everything from netbooks and industrial boxes to server workloads. Apple, meanwhile, is laser targeting high volume, premium, media heavy laptop-ish TDPs and workloads. And they can afford to burn a ton of money on die area, a bleeding edge low power process, and target modest clockspeeds like no one else can.
- The datacenter CPUs are not as bad as you'd think, as they operate at a fairly low clock compared to the obscenely clocked desktop/laptop CPUs. Tons of their power is burnt on IO and stuff other than the cores.
- Hence operating more Apple-like "lower power" nodes instead of fewer higher clocked nodes comes with more overhead from each node, negating much of the power saving.
- But also, beyond that point... they do not care. They are maximizing TCO and node density, not power efficiency, in spite of what they may publicly say. This goes double for the datacenter GPUs, which operate in hilariously inefficient 600W power bands.
Data centres want whatever gets them the most compute per dollar spent - if a GPU costs 20k you bet they want it running at max power, but if it's a 1k CPU then suddenly efficiency is more important.
It's all tradeoffs to get what you want.
They consume more only because they do not stay idle, like laptops.
The CPU cores in the biggest server CPUs consume only 2.5 W to 3 W per core at maximum load, which is similar or less than what an Apple core consumes.
The big Apple cores are able to do more work per clock cycle, while having similar clock frequencies and power consumption to the server cores, but that is due almost only to using a newer manufacturing process (otherwise they would do more work while consuming proportionally more power).
The ability of the Apple CPU cores to do more work per clock cycle than anything else is very useful in laptops and smartphones, but it would be undesirable in server CPUs.
Server CPUs can do more work per clock cycle by just adding more cores. Increasing the work done per clock cycle in a single core, after a certain threshold, increases the area more than the performance, which diminishes the number of cores that could be used in a server CPU, diminishing the total performance per socket.
It is likely that the big Apple cores are too big for a server CPU, even if they may be optimal for their intended purpose, so without the advantage of a superior manufacturing process they might be less appropriate for a server CPU than cores like Neoverse N2 or Neoverse V2.
Obviously, Apple could have designed a core optimized for servers, but they do not have any reason to do such a thing, which is why the Nuvia team has split from them, but they were not able to pursue their dream and then they went back to designing mobile CPUs at Qualcomm.