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Comment by Animats | Hacker News Reader

The CDC 6600 did that for a completely different reason. It's an early superscalar machine. It overlaps memory operations, and even some compute. This is visible to the programmer. The desired programming style is load, load, load, operate, operate, operate, store, store, store. Then the operations can overlap. There's something called the "scoreboard" to stall the pipeline if there's a conflict, but there's no automatic re-ordering.

The tiny machines at the Datapoint 2200 and 80xx level didn't do anything like that.

At the other extreme, there were low-end machines where the registers really were in main memory. The compute/memory speed ratio has changed over time. Today, arithmetic is much faster than memory, but in the late 1960s/early 1970s, arithmetic was often slower than memory on low-end machines.

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The 6600 was not a superscalar machine but simply a pipelined processor. Superscalar machines first appeared in the floating point processor of the IBM 360/91 and may well be due to John Cocke (IBM) who generalized the notion. Yale Patt (UC Berkeley, U Michigan, U Texas at Austin) refined the ideas. Most processors designed today have superscalar features.

The 6600 had multiple functional units - 2 floating point multipliers, a divider, two adders, etc.,[1] and if the instruction stream allowed it, many of them could be running at the same time. So it was a superscalar machine.

[1] https://en.wikipedia.org/wiki/CDC_6600#Central_Processor_(CP...

To be superscalar, a processor must initiate multiple instructions per clock cycle. Having multiple functional units isn't sufficient to be superscalar if one instruction is dispatched at a time. You get higher performance from the multiple functional units since the next instruction isn't blocked while the previous one is executing.

According to "Modern Processor Design: Fundamentals of Superscalar Processors", the CDC 6600 was not superscalar because it had scalar instruction issue. This book says the IBM Advanced Computer system was the first superscalar design, but the project was canceled.

This is just a definitional issue. Older thinking was that having several instructions in progress at once was enough to be superscalar. Modern thinking seems to be that you have to initiate multiple instructions on the same clock cycle. Sources differ. Here's a good overview of the CDC 6600.[1]

Multiple execution units yes, multiple operations in progress yes, scoreboard yes, retirement unit no, branch prediction no, reordering no.

[1] https://people.eecs.berkeley.edu/~randy/Courses/CS252.S96/Le...

Well, I can't stop you from using a nonstandard definition :-) The original definition of superscalar from Agerwala and Cocke of IBM was dispatching multiple instructions to the execution units every cycle. This is the same definition used by the other sources I've checked.

There are processors such as the Motorola 88100 and the Intel 80960KA that had multiple functional units and scoreboards, but were not considered superscalar. The follow-on 88110 and 80960CA processors could issue multiple instructions per clock, and were called superscalar by their creators. https://techmonitor.ai/technology/motorola_lifts_the_veil_on... https://ieeexplore.ieee.org/document/63681

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