Comment by pwg | Hacker News Reader

Comment by pwg | Hacker News Reader

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Ken, you have this statement in a footnote:

> I haven't been able to find any instruction set before the Datapoint 2200 that required memory addresses to be loaded into a register.

For a direction to look, look at the CDC mainframes (the Cybers, the 6600 and 7600 models, and possibly earlier models). A too great many years ago now while in college for my EE degree the college had a pair of CDC's (I think a 6600 and 7600, I only ever had access to the older one for a mandatory "assembly programming" class) and one of the 'quirks' of the CDC CPU design was that the CPU had (if memory serves) eight data registers and eight address registers, and to perform a memory read, one loaded an address into one of the first six address registers, which would cause a memory read from that address, storing the result in the corresponding data register (so A0 caused a read into D0, etc.).

For a memory write, one loaded an address into either A6 or A7, which caused the CPU to perform a memory write using data from the corresponding data register (A7 caused D7 to be written to memory).

The "production dates" for these CDC systems is relatively contemporary (for a reasonable fudge factor around "contemporary") with the Datapoint terminal, so these might be an example of another architecture from a similar time range (or quite possibly before) that loaded an address into a register in order to access memory.

The CDC 6600 did that for a completely different reason. It's an early superscalar machine. It overlaps memory operations, and even some compute. This is visible to the programmer. The desired programming style is load, load, load, operate, operate, operate, store, store, store. Then the operations can overlap. There's something called the "scoreboard" to stall the pipeline if there's a conflict, but there's no automatic re-ordering.

The tiny machines at the Datapoint 2200 and 80xx level didn't do anything like that.

At the other extreme, there were low-end machines where the registers really were in main memory. The compute/memory speed ratio has changed over time. Today, arithmetic is much faster than memory, but in the late 1960s/early 1970s, arithmetic was often slower than memory on low-end machines.

The 6600 was not a superscalar machine but simply a pipelined processor. Superscalar machines first appeared in the floating point processor of the IBM 360/91 and may well be due to John Cocke (IBM) who generalized the notion. Yale Patt (UC Berkeley, U Michigan, U Texas at Austin) refined the ideas. Most processors designed today have superscalar features.

The 6600 had multiple functional units - 2 floating point multipliers, a divider, two adders, etc.,[1] and if the instruction stream allowed it, many of them could be running at the same time. So it was a superscalar machine.

[1] https://en.wikipedia.org/wiki/CDC_6600#Central_Processor_(CP...

To be superscalar, a processor must initiate multiple instructions per clock cycle. Having multiple functional units isn't sufficient to be superscalar if one instruction is dispatched at a time. You get higher performance from the multiple functional units since the next instruction isn't blocked while the previous one is executing.

According to "Modern Processor Design: Fundamentals of Superscalar Processors", the CDC 6600 was not superscalar because it had scalar instruction issue. This book says the IBM Advanced Computer system was the first superscalar design, but the project was canceled.

This is just a definitional issue. Older thinking was that having several instructions in progress at once was enough to be superscalar. Modern thinking seems to be that you have to initiate multiple instructions on the same clock cycle. Sources differ. Here's a good overview of the CDC 6600.[1]

Multiple execution units yes, multiple operations in progress yes, scoreboard yes, retirement unit no, branch prediction no, reordering no.

[1] https://people.eecs.berkeley.edu/~randy/Courses/CS252.S96/Le...

Well, I can't stop you from using a nonstandard definition :-) The original definition of superscalar from Agerwala and Cocke of IBM was dispatching multiple instructions to the execution units every cycle. This is the same definition used by the other sources I've checked.

There are processors such as the Motorola 88100 and the Intel 80960KA that had multiple functional units and scoreboards, but were not considered superscalar. The follow-on 88110 and 80960CA processors could issue multiple instructions per clock, and were called superscalar by their creators. https://techmonitor.ai/technology/motorola_lifts_the_veil_on... https://ieeexplore.ieee.org/document/63681

Thanks, that's very interesting and I've updated the footnote. I looked at the CDC 6600 manual and it works pretty much like you say. If you change an address register A1-A5, the system automatically reads from memory into the corresponding operand register X1-X5. Similarly, if you change address register A6 or A7, the word in X6 or X7 is stored to memory. It is interesting to look at old systems that do things wildly differently from modern computers.

http://www.bitsavers.org/pdf/cdc/cyber/cyber_70/60045000_660...

> I haven't come across an instruction set other than Datapoint that treated register and memory accesses identically. (If you know of exceptions, please let me know.)

The DEC PDP-11 was launched in 1970, slightly earlier than Datapoint 2200.

While DEC PDP-11 also had additional addressing modes, its two most simple addressing modes, register direct and register indirect correspond exactly with the addressing modes of Datapoint 2200.

The only difference is how they were encoded. Because PDP-11 had longer instructions, they could afford separate bits for encoding the addressing mode.

So 3 bits encoded the 8 registers and a separate bit encoded whether the register is used as data (register direct) or as the address of data from memory (register indirect).

Datapoint 2200 needed shorter instructions, so they have dispensed with the bit needed for encoding the addressing mode, by using only 7 registers, so that the unused register number could be used to encode the register indirect addressing mode, where the register holding the address had to be implicit, as no other bits were available to specify it.

So what is special about the addressing modes of Datapoint 2200 is this encoding trick, which saves 1 bit of the instruction encoding with the price of allowing only one of the general-purpose registers to be used for memory addressing, while the addressing modes themselves are not new.

This encoding trick, where it is avoided to have additional bits for encoding addressing modes, by reserving some register numbers to encode those addressing modes, has been reused repeatedly by Intel when defining the 8086 and 80386 ISAs and by AMD when defining the 64-bit extension.

For instance, there are no instruction bits to encode addressing modes where the address is computed by adding a base register and an index register. Instead of that, the SP register cannot be used in the basic encoding for memory operands, so using the SP register number denotes that the address is computed by adding a base register and an index register, where those registers are specified by an extra SIB byte. There are a few other cases where some registers cannot be used with certain addressing modes, but when they appear in the instruction those register numbers mean that the operand must be accessed with some different addressing mode, like memory relative to the instruction pointer or memory absolute.

In PDP-11 terms, the Datapoint 2200 only had these "address modes" ( https://en.wikipedia.org/wiki/PDP-11_architecture#General_re... ):

    - register
    - register deferred via HL
    - autoincrement via PC (immediate operands)

No registers other than HL and PC could be output to the address bus at all. The 8080 was much more flexible, but the instructions it added weren't orthogonal, so I would say it's not at all comparable to the PDP-11 addressing modes.

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