Sparc has register windows[0] and branch delay slots[1]. The former was made obsolete by graph-coloring register allocation[2] and the latter by smarter branch predictors. It's certainly possible to design aggressive Sparc implementations, but newer designs such as RISC-V have a lot less legacy baggage.

[0] https://yarchive.net/comp/register_windows.html

[1] https://en.wikipedia.org/wiki/Delay_slot

[2] https://en.wikipedia.org/wiki/Register_allocation#Graph-colo...