Correct. The code shown is only good enough for RTL simulation. It won't help actually generate a chip with multiple read and write ports to a register file.
E.g. in this physical layout of a Swerv RISC-V CPU, the ARF section is the register file, built out of flip-flops: https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-ph....
assign rv1 = registers[rs1];
assign rv2 = registers[rs2];