Which is not to say they're not interesting questions, but the answers will not be actionable information without the aforementioned money and people.
It's a bit like a single carpenter asking about how you get a permit to build a skyscraper.
I manage products on the board level, never been down to chip design. Are there design agencies/firms who are familiar with the processes (but are not fabs) that can be engaged to help de-risk your design / assess the manufacture-ability of your chip?
You could interpret your original post that the customer-side of things is a foregone conclusion (as in you've talked to a lot of prospective customers and you have high confidence your product will sell), now you just need to focus on designing the product. Is that the case?
If you've talked to customers and have high confidence, why not raise money on the basis of a compelling product?
Setting that aside, if you have some revolutionary design for an architecture, that should already be abundantly clear from emulating your designs on FPGA. If you aren’t completely sure (and have evidence to prove) that your design is significantly better than anything that has been made before, you’re not at the stage where you should be thinking about manufacturing a chip with modern hardware. As was said elsewhere, making a chip is a phenomenally capital intense process so if you’re planning on competing with any existing hardware you’re going to need to justify that investment with radical gains, not incremental improvements. If you have an idea which you think could speed up existing hardware, your best bet is to work with/sell IP to companies which already design that hardware since it’s just not worth the investment needed to start a whole new chip company for a potentially 10% better CPU/FPGA.
> General purpose processors and FPGAs are entirely different
Sure, but I specifically want to research the optimal intermediate point between classical CPU architectures and classical FPGA architectures.
Why not? There are plenty of open source RISC-V soft CPUs available for you to run on the same FPGA to benchmark against. If its the architecture which is special it doesn't matter if it competes against top of the line chips, just that it beats out everything comparable. You don't need to prove that your design will beat out a similarly designed chip on advanced silicon, just that your design implemented in the slow FPGA is better at something (not necessarily everything) than a CPU trying to emulate the same behavior. Having the PDKs won't help you much either, since on top of that it will take hundreds of thousands of dollars (minimum) in software costs and teams of people to help fine-tune and simulate such a large design. Doing this without the intention to eventually tape-out that design is a massive waste of resources.
I understand where you're coming from but the point of getting access to those PDKs isn't for rapid prototyping. The value proposition of your design must already be clear before beginning to design for a specific process. If you can't prove that your design has significant advantages that no chip in the next few years can possibly compete with, then there's just no point in attempting to design, synthesize, and simulate it on advanced nodes. That process is a significant investment in itself and if you're unsure enough about the potential benefits that you need to know exactly what it would look like in reality, then it's just too risky to spend the years it will take to get a working chip which may already be outclassed by the time your first chips come off of the line.
> Sure, but I specifically want to research the optimal intermediate point between classical CPU architectures and classical FPGA architectures.
That sounds cool, but this makes it sound like you're a really long way off from considering the specific characteristics of a given process node. Focus on designing an architecture which does something better than current designs can possibly do, such that the value of implementing it in a chip will be unquestionable.
> You don't need to prove that your design will beat out a similarly designed chip on advanced silicon, just that your design implemented in the slow FPGA is better at something (not necessarily everything) than a CPU trying to emulate the same behavior.
No, I do. Since, again, my objective is creating actual chip, not a soft processor.
Fine-tuning will come only after it's clear that the design is good.
I just don't see a way to create such an abstract model which will have any utility for measurement.
And the advantages depend on actual implementation, which depends on process parameters, and if I try to make a design which is good regardless of actual parameters, this will be too conservative and I may not succeed.
Edit: s/dabbing/fabbing/ lol
DM to where?
Why do think your architecture needs pdk information? You should be able to show a _massive_ improvement at the logic gate level, then get funding to hire a security team which would let you pass the fabs audits
If I make only a gate-level model, I have no idea how to prove the benefit of my design, short of just showing it in entirety.