I understand you. I had same thoughts.
Yet I posted this because-
- Book is really good for learning RISC-V Assembly.
- There are plenty other RISC-V simulators. Use what you like.
For learning each instruction one by one, I like the following sim.
https://www.cs.cornell.edu/courses/cs3410/2019sp/riscv/inter...
or read more here:
https://medium.com/swlh/risc-v-assembly-for-beginners-387c6c...
- RISC-V has very small number of instructions (less than 100, the integer version has less than 50), compare this to ARM, X86 etc. By the way, word "REDUCED" in RISC does not mean less number of instructions in ISA. Rather it means, each instruction has significantly "REDUCED" functionality such that, it can be easily executed in single clock cycle, can be implemented with less gates, easy to build pipelines, easy to add super scalar units etc. overall simplicity is main goal to get multitude of benefits. Yet, I see, even ChatGPT told me that other way around until I pointed that ARM ISA (being RISC) has significantly higher number of instructions compared some other CISCs. I guess why it failed to understand a fundamental concept of computer architecture that it is running on. May be, corpus of text it trained. It is a irony, yet we are told, AI can think (I still use AI!)
However, it told one thing very correctly: All RISC-V have Load-store model, where entire ISA can be devided into 2 parts: First part, instructions that purely work on cpu registers without ever making memory access. And second part, where instructions that only access the memory. This is fundamentally load store architecture which is one of the must part of RISC-V. But load-store can also be used in CISC.
Correct me if I am wrong here.
Last but not least:
If I can turn time back and learn programming language,
I would learn RISC-V assembly, ( not C or Python or JavaScript ...).
In that sense, I am learning RISC-V and sharing it to others.