What is a node in this context and what does designing a new node entail? Does this design process mean TSMC can do something with ASML machines that another company with the same machine couldn't do?
The ASML machines perform the actual photolithography. They expose the die mask to the photoresist coated silicon wafer. Using that technique, you can built up complex 3D materials incorporating different layers and shapes. But the ASML machine doesn’t know how to make a transistor. It’s kind of like a 3D printer in that way.
That's not quite how design works; it's much much more detailed. At the end of the day, TSMC's customers send them a "GDS" file that is a complete physical representation of the die they want manufactured. It describes every top-to-bottom later of the manufacturing process. (TSMC will take the GDS layers and split them up or combine them or do other operations, depending on some process details, but the customer will also check and sign off on that).
It's not just telling TSMC where to put standard cells or SRAM. And while TSMC does offer their own standard cells and SRAM, customers can and often do design and use their own. Analog/RF design is even more detailed, since that's done at an individual transistor level.
TSMC is mainly in the business of design and selling a manufacturing process for making transistors not logic gates.
For analog/RF design, of which there is still an enormous amount, it's always transistor level.
That being said, there is a little room for tweaking. The manufacturing process has a ton of variation in it, and the center point / average of that variation can be moved around a little. I think most companies just take what they get, but I'm betting the big players (Qualcomm, Apple, Nvidia, AMD) all do internal tracking of the process variation when they get product back, and give feedback to the foundries to make changes to optimize their own yield.
There's also been a recent push in the very new and advanced processes for "Design-Technology Co-Optimization", where the digital circuit design (i.e. standard cells and memory) and the process technology design happens together. We got here because all of the low hanging fruit has been picked and now companies are chasing single digit percentages in yield and PPA (power, performance, and area) improvements. It's a collaboration between foundry and customer that happens before the process is even released, so again - big players only, and it's still more tweaking than custom transistors.
For other types of processes, meaning non-bulk CMOS, customers can definitely design their own transistors. This is especially common in RF applications where you're often making chips with a few transistors. In some cases, it can be just changes in the shapes and/or dimensions of the transistors in the GDS, relative to what the foundry recommends. For this type of custom transistor, the foundry still controls the material science details of how the process happens. In other cases, though, customers are in control of everything from the transistor dimensions to the chemical concentrations and methods used for fabrication.
Like a bus stood vertically on its nose.
Does that expansion of the analogy work or did I just move the analogy further from the truth?
For example, when you're making a cube, the sharp ends are places where bad things happen. When making sharp movements, the nozzle will tend to leave ugly trails and in other times cause warping. So here you can do a trick to save yourself: mouse-ears (extra material around the important edge, so that the bad artifacts happen instead on additionally-created non-core-geometry). At ground level, you use brims.
TSMC had previously used a "spin-on" dialectic technique at a previous node, and reverted to CVD because of problems.
They were able to beat all other manufacturers to market with copper interconnects (including IBM), because they avoided spin-on, which worked well in testing, but not in production.
They had great luck in gaining this prior experience.