I don't understand the significance of this. Tried to read up on what PHY refers to, but didn't connect the dots. How will this make progress?
Think for example a standard SoC chip for an embedded device scenario - it will have one or more MII ports [1]. Onto these MII ports, you can then attach a PHY chip for your needs... Ethernet, coax, fiber optics, direct connection, whatever, so you don't need to change your SoC chip or even your operating system just if you want to offer a product with Ethernet and fiber networking.
Usually, these chips are proprietary... but this project provides an open source implementation, so that in the worst case of no one producing Ethernet PHYs any more, you can take an FPGA instead.
[1] https://en.wikipedia.org/wiki/Media-independent_interface
Normal logic pins on FPGAs generally can’t be used to transmit or receive fast enough (not to mention some of these standards are using multi-level signalling like PAM-4 which a normal logic pin just can’t do).
100Mbps on the other hand (like this project is doing) is possible to produce, but I do wonder how likely it would be to be able to practically receive with any meaningful cable length without an analogue front-end that you find in a PHY.