I will disclaim that I have no idea how Oxide is using P4 for packet processing, but what you are currently doing with P4 on your switch can likely be moved to some rules on a dumber switch/router (eg what hyperscalers use) plus a special packet encapsulation on the NIC using similar P4 rules. That lets you push the intelligence out of the switch and toward the edge of the network. At least, this is the approach that the major hyperscalers are taking, and there doesn't seem to be a good reason to not do this (other than potentially the cost, since you don't have the scale to get a good discount on the NICs).
Didn't they mention in the talk that the Smart NIC is the limiting factor? Likely would also be hard to have open source code on a Smart NIC.
That switch chip likely isn't anywhere near open-source either. The P4 rules don't have to use proprietary features or break NDAs.
Yeah, definitely not a switch ASIC. But would love to see something like the E2000 with 1) an open underlying ISA to enable truly open P4 compilers and 2) no compute complex so we can focus the power budget on the programmable data plane.