To be clear, you don't get all three.
Also, are these Apple's numbers? They are better than what TSMC say (1st gen) 3nm silicon provides:
> N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology
https://www.tsmc.com/english/dedicatedFoundry/technology/log...
Actually you do. The branding is called FinFlex, but the upshot is that you can use different FETs for different parts of a circuit. So some critical timing bottleneck blocks could be built with performance optimized FETs and other blocks can optimize for low power.
The numbers from TSMC for N3E are +18% speed improvement at same power, -34% power reduction at same speed, and 1.7x density improvement.
https://www.tomshardware.com/news/tsmc-outlines-3nm-roadmap
>Also, are these Apple's numbers?
Ha ha. That's funny. Does Apple ever release any numbers prerelease?
Hope it's obvious, but no, they are not Apple's numbers—this is a rumor about unreleased products.
'70% logic density gain' sounds like 'reduce area by 35%' to me
The only one that might not line up is 'reduce power consumption by up to 50%' vs 'up to 30% power reduction at the same speed as compared with N5 technology'
...but you have to know what's being compared before deciding the numbers do (or don't) make sense
Typically, sram (cache memories for example) doesn't scale as much as core logic, and interconnect (connections between the cores, DDR, etc...) almost don't scale at all.
This is highly dependent on the design of the SoC, but the core logic is rarely the largest of the three, so you will not see a 35% reduction of the total area of the chip: only of the areas the most densely packed with logic. What you could have for example is a 35% more powerful neural network accelerator in the same area as the previous generation. But you will not have 35% bigger cache.
N3 is a stop-gap as TSMC is behind on their N2 GAA process. It's not so different from Intel's 14nm++++++ where it was dramatically better than before, but still not enough.
No, but improving density still makes it smaller (for an otherwise-"identical" offering) :)
Can you elaborate?
Start with processor pipelining, branch prediction, speculative execution, etc
Then move to multiple CPUs/CPU cores
A practically-linear program (ie hardly any unpredictable branching) can be run ~5x faster on a 5-stage-pipelined CPU than an unpipelined CPU
Liekwise, parallelizable tasks can benefit from multiple CPUs/cores, whereas non-parallelizable tasks will not (much)
And then you have performance-per-watt vs raw hertz count: today, most people seem to care more about performance-per-watt than raw "performance"
Ie, ceteris peribis, a 30w 4 core CPU at 1Ghz is going to be more favorably viewed than a 100w 6 core CPU at 1.8Ghz - you can throw 12 "low power", "slower" cores at the problem for ~10% less power draw than the "high power", "faster" cores
Then you can also look at the relative efficiency of different CPU platforms and/or microcode changes in a single platform: that was the major selling point of Apple's anti-Intel ads 15-20 years ago - the PowerPC was "faster" than the Pentium because it was "more efficient" at several families of tasks (even though the raw clock speed of the PPC was typically lower than the comparable Pentium offerings)
This comes up with the Apple M-series CPUs vs the Intel chips they replaced - they may not be "faster" (in raw ghz), but they're more performant