TinyEMU – x86 and RISC-V emulator, small and simple while being complete
bellard.org
bellard.org
> 4.1) 128 bit support
> The RISC-V specification does not define all the instruction encodings for the 128 bit integer and floating point operations. The missing ones were interpolated from the 32 and 64 ones.
> Unfortunately there is no RISC-V 128 bit toolchain nor OS now (volunteers for the Linux port ?), so rv128test.bin may be the first 128 bit code for RISC-V !
Although with my pedant hat on: that's extrapolation, not interpolation. That's because 128 is outside of the existing range.
> An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor.
> Selfie is a project of the Computational Systems Group at the Department of Computer Sciences of the University of Salzburg in Austria.
The BL808 is actually a 32bits risc-v as a main core with a 64bits risc-v core on the side (convoluted hardware programming from the 64bits risc-v core).
The K210 does not seem to have a USB controller (only a UART<->USB dongle).
Then I am lurking on some mango boards, with a D1, the D1 being completely overkill.
Anything else?
I haven't been able to boot mine. But I have no UART adapter to see whats wrong.
I could not confirm if the k210 has a usb controller (not the UART<->USB dongle).
Lichee RV (with a breakout dock board) is the one I have.
I assume the RISC-V emulation is all VirtIO based and not real...
The RISC-V crowd hates bitwise anything.
It is considerably newer than every extension this emulator implements, and thus reasonable it'd have these and not B.
[1] https://github.com/riscv/riscv-bitmanip/releases/download/1.... from https://github.com/riscv/riscv-bitmanip/releases . [2] https://courses.cs.washington.edu/courses/cse481a/20sp/notes... [3] https://wiki.riscv.org/display/HOME/Recently+Ratified+Extens...
Even the newer revisions of cores that have been available for a while (like SiFive U74) have been updated with B support.
As such, I believe it to be a non-issue. Hardware simply takes time.
>which are difficult to prove their value as a result,
As with any RISC-V extensions, each instruction had to meet many criteria to be allowed in there.
Rationale accompany the instructions in the documentation.
That's fantastic.
> Rationale accompany the instructions in the documentation.
I've read it-- I didn't personally need it to be convinced, but I'm surprised it convinced vendors. Glad to hear that it has.
edit: Zbs.
That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)
Hopefully together with V.