How the death of SRAM will affect the future of PCs | Hacker News Reader

How the death of SRAM will affect the future of PCs

xda-developers.com

16 pointssroussey15 comments

Here is a link to the WikiChip article mentioned by the XDA article.

It's a bit more technical and has some pretty nice graphs showing information about the different densities of SRAM at each different node/fab size.

https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-wi...

Thanks! Discussed here:

The Death of SRAM? - https://news.ycombinator.com/item?id=33990408 - Dec 2022 (70 comments)

Sweet, thanks dang :)

> TSMC's 3nm process showed practically no improvement in density over the company's previous 5nm node with respect to SRAM density

SRAM is becoming a larger and larger percentage of area of many chips from both a need for more cache and from the fact that everything else is shrinking.

This also makes for very expensive SRAM (paying for cutting edge 3nm pricing but only getting 5nm product). AMD is ahead of the curve here with their 3D cache, but that only helps L3+.

Is it likely they'll just offload the entire L3 onto a larger node sized chiplet to save both space and money? If 5nm and 3nm are the same SRAM size, no sense putting any L3 on the 3nm if the latency impact isn't too major.

In principle SRAM is just flip-flops, and flip-flops are just logic. I realize that in practice SRAM isn't implemented quite this way, but if logic transistors continue shrinking, maybe it's time to think about doing so?

It's not that simple. Large SRAM arrays have the same problems that DRAM has: how much charge do you need to drive into the row and column lines to select the cell you actually want to have active. You can't push it too high because then power consumption goes bonkers. You can't make the wires too small because then they can't pass the power required to drive the entire array. In short, hardware is hard with designers needing to make crazy multidimensional tradeoffs.

So we one more step away from SMT, and next generations will be more and more NUMA.

Good article I would still prefer that they would put the 3nm in quotation marks.As great as the advancements of TSMC were over the last decade their naming scheme is anything but and it's also not in relation to their actual node size anymore.

Sorry, what? I feel that point has been slipping past me. Are you saying that 5nm doesn't mean 5nm, and that 3nm doesn't mean 3nm? As in, the name no longer relates directly to the sizing?

That has been the case for a while.

Welcome to marketing!

It's not just TSMC, all the silicon fabs, their "node size" is a methodic yet arbitrary decreasing number.

They do mention that after 32nm they name of the process node is meaningless.

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