The Death of SRAM?
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The main problem with scaling is that SRAM found an optimal layout in FinFET with no significant wiring issues. While scaling from 7nm on down none of the tricks that benefit logic density - fewer lines, reduced gaps, contacts over active gate - SRAM does not need them. It was already optimal. The only thing it benefits from is honestly finer features, which is happening only slowly.
The next major jump expected is CFET where going vertical is matched by a new optimal pattern that takes advantage if the N and P being above each other. That is generally expected for N2/20A processes.
That's not going to happen because the process tech for dram is tuned for capacitance and the process tech for SRAM and CPUs is tuned for speed...
How about, "this CPU is using 3D nandram and is rated only for one quadrillion instructions or one year whichever one comes first!" Imagine a compiler that has to do wear-leveling on the registers!
6T SRAM has a lot of issues in leading-edge process nodes that are optimized for logic, since it depends a lot on the analog characteristics of the transistors used. Separating SRAM and logic processes will eventually make sense if we find that SRAM and logic can't scale on the same process.
L1 and L2 caches on the logic die can be 8T SRAM (which is, I think, already in the L1 cache of Intel CPUs) if needed.
Betteridge's law strikes again.
There's a reason magnetics were popular when circuits where finger-sized, and completely disappeared when they got smaller. It may not be impossible to make 3D magnetic circuits that match 2D electronic ones, but it's very close to that.
It’s a very nice embedded flash replacement though…
For something like a cache on a CPU (the main use of SRAM), what's the purpose of it being non-volatile? SRAM doesn't need refreshing, and it's a relatively small percentage of total power.
It sounds like it would be chosen for other reasons, and there would no purpose for the non-volitiliy beyond it being a nice-to-have in some weird scenarios.
Sort of like using core as main memory. That was just the main memory technology of its day, it happened to be non-volatile, but that wasn't it's main selling point.
SRAM has desirable properties; simplicity, self sustaining state, latency.
The flattening curves follow the approach to the physical limits of doped silicon. It'll be interesting to see if another electron based but different semiconductor or another method of computing entirely (maybe photonics or some other range of the EM spectrum?) continues the rise in density or if we instead focus more on optimizing hardware and software.
You're no longer competing for space on the same die as the functional units.
> These would use one or two "Zen 4" chiplets with stacked 3D Vertical Cache memory. A large amount of cache memory operating at the same speed as the on-die L3 cache, is made contiguous with it and stacked on top of the region of the CCD (chiplet) that has the L3 cache, while the region with the CPU cores has structural silicon that conveys heat to the surface
Source: https://www.techpowerup.com/301721/amd-readies-16-core-12-co...
Not from the benchmarks I've seen. Most games, perhaps.
The reason they didn't do it in the right order to start with is that the top die cannot be designed to work both with and without the cache. They can only start stacking the cache below the cpu once they accept that every single product will have a stacked cache.
9 speed was already almost too much for a 'casual-enthusiast' [0].
But in general, Shimano or Campy is my preference for drivetrain [1] and Avid/Shimano for brakes [2].
[0] - I've blown out 9 speed cassette in less than 1k miles due to my riding style (skipping gears). NEVER had a similar problem on the 8 speed cassettes or 5 speed freewheels I would roll on.
[1] - Ok so I had a SRAM grip-shift break in a way it shot plastic in my face which was a terrible first impression. But also I've had 'issues' with a lot more SRAM vs Shimano when building/maintaining bikes. And then there was the Truvativ 3 speed road crank that could never get adjusted right (FWIW, I got the same 'model' as a double for a tandem and it was bliss... but that is my point about QC.) Also, that mess that was 'power spline'. Tore that up before in less than 500 miles.
[2] - In the day I was all about Speed-Dial 7s[3] for levers and BB7s for brakes (Very adjustable, none of the pains of fluid based disc brakes) and Shimano had a bad habit of trying to make things proprietary (center-lock disc hubs).
[3] - SD7s are the best retrofit-bike thing on the planet, because they can make all sorts of old/new brake combinations work with a consistent set of levers!
A SRAM cell is 6-8 transistors all connected internally with only a read and data line coming out (well, and the power rails). That's already horizontally packed, making the transistors beefier won't help anything.
- Remove all or almost all L3 from the CPU die built with the best available logic process, like N3E
- Stack a last level cache die with relatively cheaper process that has similar or better SRAM density, like N5
For example, with the M1, Apple tied the DRAM interface to the CPU. That got them more bandwidth, but then you can't upgrade the memory, which is weak.
But why not do both?
Have e.g. 8GB of high-bandwidth DRAM soldered to the board, essentially that amount of L4 cache, but keep the DIMM slots where you can add arbitrarily more memory with less bandwidth.
(They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)
And already now you have NUMA where performance is different and depending on which core you are.
Processors can use the L2 cache from other (remote) processors before reaching out to DRAM.
) Although signs of slow down were plenty beforehand if you squint your eyes it was possible to attribute it to Intel dropping ball and rest of industry catching up its 1.5 generation lead. (Industry converging back to long term trend).
That said, there are exciting things in stacking layers, and inter chip layer connects (chip on chip technology) that could make more feature dense (if slightly taller) chips.
Heat dissipation continues to be an issue as well.
As someone who started at Intel in the 80's though, the amount of "surplus" cheap resources resembles your typical laptop with gigabytes of RAM and terabytes of disk, there is a huge amount of gain to be had in re-architecting software as there is gain to be had in re-architecting the micro-architecture of SoCs.
Similarly, what would it look like if we dedicated CPU cores to running the kernel and other cores executed the kernel through io_uring and futexes only. That could significantly reduce cache pollution although there may be more cross cpu cache shoot down?
Just for context, most L3 caches today are the size of the entire RAM from 20 years ago. You’d think that you should be able to run the hyper visor totally out of L3 cache.
Also some of these alternate architecture would also be inherently more secure because it would be harder to exploit side channel attacks across contexts.
DRAM, for example, cannot be shrunk because the capacitors that enable DRAM physically cannot shrink and still function properly. SRAM is just six transistors wired to store a bit. There is nothing stopping the use of chiplets manufactured with different process nodes... AMD already does this.
SRAM cells are constrained by certain features that are not able to shrink much https://semiwiki.com/forum/index.php?threads/sram-cell-scali... the logical schematic of an SRAM does not show anything about how a real cell is physically constructed. Foundries and high end design companies have teams doing SRAM design.
Yep, this is also why the claim in this article title might just be a bit overstated. There's a mention that TSMC will likely announce optimized SRAM cell designs for N3-like nodes at some point, and these designs can be expected to involve some scaling.
Also known as NAND flash, i.e. the chips that actually wear out. Another example of planned obsolescence creeping in to what used to be effectively unlimited lifespan for "solid state" electronics?
You have:
- EEPROM for low/medium frequency of update, small size, persistence
- NAND flash for low/medium frequency of update, semi-arbitrary size, persistence
- eDRAM variants (Mosys '1T SRAM' comes to mind, which is still DRAM but has more dedicated Row/Column circuitry vs SDRAM's RAS-CAS timing shenanigans) for frequent update, volatile or maybe battery backed storage, non-persistent
Which... we -kinda- see in some layers already, as eDRAM has gone from 'fancy server procs and halo mobile chips' to a -little- more mainstream.
But more on point, this article's context is static ram on-die for a microcontroller or similar. One possible replacement for SRAM is magneto-resistive RAM (MRAM) - it's not quite as fast as SRAM but close enough for many applications, it's higher density than SRAM, so it'll take up less die space, and it's non-volatile so µCs can ditch the NOR flash often used for code storage.
One great thing about MRAM is that it has no write wearing: it has an effectively unlimited lifespan, without all the downsides of magnetic tape. I look forward to seeing it (or similar technologies) in microcontrollers in the future.