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Comment by Animats | Hacker News Reader

All that chip stacking. How do you cool it? What's the yield? This is packaging, not higher density transistors.

Cooling is probably less of a problem than many people think. Modern cpus are (or rather would be) very efficient, if you don't push them to the very end of their frequency-power bathtub curve, but the latest generations of desktop cpus are basically stock overclocked. They can achieve 80% of their performance at 40% the power. That basically means you could double performance by 2.5x-ing silicon for the same power/heat.

Sounds exactly like the giant core count server chips; well they're still a little overclocked but not nearly as much.

A major issue is the vast quantity of state machine dependent programs, like videogame servers, more simply coded data processing generally.

Games and other simulations generally are often single threaded since they're engineered as iterative processes rather than parallel expressions due to possible conflicts in state propagation.

>How do you cool it?

I've wondered whether little micro-filament heat pipes sandwiched right into the chips might be possible, all plumbed into a heat exchanger on the side of the die that can be directly cooled, facilitating the extraction of heat from deep within the stacked chips.

> I've wondered whether little micro-filament heat pipes sandwiched right into the chips might be possible

Maybe; there's https://www.tomshardware.com/news/tsmc-exploring-on-chip-sem... from about a year and a half ago.

Interesting, thank you!

Direct water cooling huh. With channels right in the silicon I imagine water purity is just that much more important.

God help you if the water gets gunked up with disintegrating gasket material[0] and blocks some of those channels off, or even worse, conductive stuff.

[0]https://www.youtube.com/watch?v=jHdEqWpexH0

I don't know about production chips with such things integrated, but it's certainly been tried. The below article is from 2008.

https://www.eetimes.com/ibm-git-demo-3d-die-with-microchanne...

Someone needs to invent a diamond layer between stacks! High thermal conductivity with virtually no electrical conductivity, which is unusual as thermal and electrical conductivity usually go hand in hand. Diamond would be perfect to transfer heat out of densely stacked chips.

A lot of it is just two layers - the chip and the interconnect below. If you have a chip that generates a lot of heat, you can stack another one that generates less heat on top of the hot one and use it as a heat spreader (a lot of mobile chips are like that). Also memories have only a small part of them being used at any given time, so they are a good fit for tall stacks (current flash memory does that too)

Not sure if relevant but dram refreshes continuously.

On-die CPU caches typically use SRAM. Modern DRAM chips are already die-stacked in several layers. But maybe DRAM is more heat sensitive than SRAM, so more difficult to stack atop a stronger heat source?

IIRC, the RPi SoCs have a DRAM chip stacked on top of the processor.

> How do you cool it?

That's the million dollar question that we're trying to solve right now.

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