op src dest
is the logical order, the rest of the syntax I don’t care about much.At least the Intel one makes actual mathematical sense: `section:[base + index*scale + disp]`
The only reason “AT&T syntax” exists for x86 is because people working at AT&T refused to use Intel as the authoritative reference on the syntax, and, instead, decided to follow the convention of the PDP, Motorola, etc. family and friends. Hence why `as` (and subsequently `gas`) have that as the default.
That is logic.
Ergo op src dest
"Add 4 to x and store result in x" vs "Let x be x + 4"?
So "add 4 coins to that bucket", generally means at the end of that operation the bucket contains at least four coins plus any coins that were already in the bucket.
You know what the logical convention to use would have been? The order that every assembler on the planet already used.
I quite like the SSA style which tends to be dst0 dst1 opcode src0 src1 but that doesn't model assembly brilliantly. Perhaps that order with read-write arguments required to appear on both sides of opcode with the same symbol has some merit.
They're using a dollar sign for immediates.
As if you can't notice that it's a number.
addl $4, %eax
that's 3 different completely unnecessary symbols for things which are not ambiguous in the first place:- the operation width is provided by the registry
- a number is an immediate
- a register is named
Hence the much less noisy Intel syntax:
add eax, 4 add $4, %eax
- is fineCompare with
add 4, %eax
The "less noisy" Intel syntax becomes: add eax, DWORD PTR [4] add eax, [4]
if you desire. Indeed, many disassemblers will follow suit in unambiguous cases. IDA, for example, does this. add eax, [4] ; inferred
add [eax], 4 ; ambiguous
add DWORD [eax], 4 ; explicit
A disassembler may output it when not necessary, however.https://blog.yossarian.net/2020/06/13/How-x86_64-addresses-m...