A mass misbelief in the continuation of Moore's law into impossible sub-molecular scales. There is no more low-hanging fruit of "just make the optics more precise to make the lithograph smaller"; every process-node step we're taking now is rather a "side-step" involving solving increasingly-complex puzzles to make the same-sized features do more per molecule. It's code golf, at a hardware level. And as in code golf, there's a pretty low ceiling as to how intricately interwoven features can become. You can't eliminate the fundamental need to have all those features in the code (circuit) in some sense.

The actual visible effect of this is an economic one: we've gone from spending linearly more marginal CapEx per fab process-node upgrade, to spending geometrically more marginal CapEx. Each process node under 8nm has been twice as costly to design as the one before it. This is untenable.

The particular measurements of the elements are not interesting, but the transistor densities are meaningful. I would expect a 1nm chip to achieve densities 100x a 10nm chip. That seems unlikely.

The active part of a FET is the area that is under the gate or surrounded by the gate.

It makes no sense to speak about a transistor that would be smaller than the gate, there is no such thing.

Besides the active part, whose conductance is controlled and variable, the transistor includes parts that are either electrical conductors, like the source , the drain and the gate electrode, or electrical insulators.

While those parts may be less important than the active part, they also have a major influence on the transistor characteristics, by introducing various resistances and capacitances in the equivalent schematic.

What matters is always the complete transistor. The only dimensions in a current transistor that are around 1 nm are vertical dimensions, in the direction perpendicular on the semiconductor, e.g. the thickness of the gate insulator.

The 2D semiconductors that are proposed for the TSMC "1 nm" process are substances that have a structure made of 2D sheets of atoms, like graphite, but which are semiconductors, unlike graphite, which is a 2D electrical conductor.

In this case the thickness of the semiconductor can be reduced to single layer of atoms, which is not possible with semiconductors that are 3D crystals, like silicon, because when they no longer form a complete crystal their electrical properties change a lot and they can become conductors or insulators, instead of remaining semiconductors.

There is little doubt that for reducing the transistor dimensions more than it is possible with a 3D semiconductor like silicon, at some point a transition to 2D semiconductors will be necessary. It remains to be seen when that will be possible at an acceptable cost and whether such smaller transistors can improve the overall performance of a device, because making smaller transistors makes sense only when that allows a smaller price, smaller volume or higher performance of a complete product.

Isn't the gate part of the transistor? Or can I pack multiple FETs with a common gate in denser?

Investors. Even more sophisticated investors can be bamboozled by various claims. Because investors are usually trying to pick the future winners, they need these things as proxies to determine who is actually going to have the faster chips, or the lower costs, etc.

Analysts are often not from the exact line of business. They may have a bachelor's in engineering, or something, but they're usually not domain experts beyond having studied the field from a business perspective and gotten used to its lingo. So, these things can be kind of manipulative. That said, it's par for the course. It's better than outright lying and bribing the analysts like in the 2000-2002 telecom bust.

Since when is it acceptable to trick laypeople, especially when laypeople are buying products with the false advertising (cpus...)?