They're more like microcontrollers with a small CPLD peripheral. Not enough programmable logic to implement an interesting IP core, last time I checked.

It is FPGA technology alongside analog blocks as well as other pre-defined peripherals available from the design tool. Most pin are unallocated and you drag and drop gates, ADCs counter etc etc and wire them up. If a block can be software controlled it is addressable via the ARM core and one can read hardware state in software.