I don't think it would be. You'd have to detect them on the data bus and also differentiate between data and instruction accesses which I don't /think/ the Z80 does, at least not easily.
6502 doesn't have a pin for "IO space" but you just pick your MMIO range e.g. 0xCnnn on the Apple ][ and a NAND gate on the 2 MSBs and a 3-input OR/NOR on the output and the next two bits gives you effectively the same signal. (or an OR gate on bits 12&13 plus a 3-input AND/NAND on bits 14&15 and the output).
It was common to use 6522 VIA 8 bit output ports to bank switch one or two 4k ranges to allow each such 4k range to access 256*4k = 1 MB of RAM. You could use a 16x8 bit SRAM to do the same thing for the whole address space.
Zilog actually designed their peripheral chips to handle the RETI (return from interrupt) opcode specially. On the Z80 itself it does the same thing as a normal RET, but other chips can detect it on the bus and treat it as the signal that their interrupt handler is finished.
I also recall reading about some hobby project to add a PC-relative addressing mode to the 8080 or Z80. A redundant opcode like "MOV A,A" would be used as a prefix, which caused the external hardware to add the program counter to the immediate operand of the following instruction. Can't find it right now.
I guess it’s a short step to looking up memory addresses against a bitmap for validation. I couldn’t tell from the video if this is what he did. Cutting the addresses into pages would let you save or add more levels and I guess you could implement a TLB similarly.