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I think Gustafson may be the kind of liar that doesn't know he is lying. He knows saying that his design improves upon power and die size sounds good, so he says it.

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Nope, I have seen it tested on an fpga, many years ago. The reference was Berkeley hardfloat. This might not be the best implementation ever, but it is the most accessible open source one.

Where do you save transistors? With the Posit you have to be able to deal with larger mantissa, multiplier size scales with mantissa bits squared, so even a small increase makes quite a mark.

Maybe you save a bit by not having denormals, but then parsing the packed float is a bit more complicated in that the bits do not have a fixed division between exponent and mantissa.

It is possible that the Posit circuit was smaller by leaving out some feature, like exact rounding, which is quite expensive, but then it is not an apples-to-apples comparison.

you save transistors but not dealing with NaNs and Infs also. you also save some because your comparison operations just use signed integer comparison so you don't need hardware to do those. my guess is that when you combine these effects it could be a net win for 16 bit. also bigger multipliers might be slightly sub-quadratic by using karatsuba or similar.

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