> Sadly, Qualcomm was very bad at implementing caches, but that’s a story for another day.
Anyone know what that story is?
Anyone know what that story is?
They do have 3 cycle L1D latency, but again that's at low clocks, and it's a 24 KB L1D so it's 25% smaller than most L1Ds we see today. Not great considering you're eating 20+ cycle L2 latency once you miss the L1D, unlike most CPUs today that have 12 cycle latency for 256 or 512 KB L2s.