One of the reason's Apple has such a big lead, according to all the discussion I've seen here on HackerNews is that it's because Apple is on a newer chip process (5nm) whereas everyone is behind, and that if the competition was on a better process the differences wouldn't be as stark.
The reason Apple is using a better process is they are investing so heavily in TSMC so that the process can be improved, and for that investment they get sort of a "dibs" on production, which, honestly seems fair. It's not like Apple sees TSMC as a charity here and I don't think anyone could argue otherwise. Also, as is probably obvious with Apple using these chips in iPhones, iPads, Apple TV, Watches, and now Macs (A series, M series, etc) they might be one of the largest single customers of TSMC and to even be able to produce enough of those chips they need to buy production well in advance.
I don't know, people can claim unfair advantage all they want but looking at it from a business standpoint Apple is moving things forward.
Apple is already the single largest company in the world. What would it take for you to admit they're abusing their market position?
All the normies would have been given ideas by the A7, the first 64 bit design. I think that's when the iPhone benchmarks really started pulling well ahead. It's not like Apple didn't telegraph their move almost a decade in advance. I'm not sure what you're suggesting.
It’s not like Android is backed by a tiny startup.
But more to the point, what does an article about ARM suing Qualcomm have to do with Apple?
More than someone simply claiming it. Loudly proclaiming it in a comment isn't showing your work. This is like math class, show me the work.
How are they abusing their market position?
It's a reason, but far from the only reason.
Go back and look at the comparisons between Intel and AMD's x86 cores vs. Apple's Firestorm big core at the M1 release.
Apple devoted much more die size to decode, execution units, the ability to reorder instructions, and cache, for instance.
>What really defines Apple’s Firestorm CPU core from other designs in the industry is just the sheer width of the microarchitecture. Featuring an 8-wide decode block, Apple’s Firestorm is by far the current widest commercialized design in the industry.
Other contemporary designs such as AMD’s Zen(1 through 3) and Intel’s µarch’s, x86 CPUs today still only feature a 4-wide decoder designs (Intel is 1+3)...
https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...
>On the Integer side, whose in-flight instructions and renaming physical register file capacity we estimate at around 354 entries, we find at least 7 execution ports for actual arithmetic operations. These include 4 simple ALUs capable of ADD instructions, 2 complex units which feature also MUL (multiply) capabilities, and what appears to be a dedicated integer division unit.
https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...
>A +-630 deep Reorder Buffer is an immensely huge out-of-order window for Apple’s new core, as it vastly outclasses any other design in the industry. Intel’s Sunny Cove and Willow Cove cores are the second-most “deep” OOO designs out there with a 352 ROB structure, while AMD’s newest Zen3 core makes due with 256 entries, and recent Arm designs such as the Cortex-X1 feature a 224 structure.
https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...
>On the cache hierarchy side of things, we’ve known for a long time that Apple’s designs are monstrous, and the A14 Firestorm cores continue this trend. Last year we had speculated that the A13 had 128KB L1 Instruction cache, similar to the 128KB L1 Data cache for which we can test for, however following Darwin kernel source dumps Apple has confirmed that it’s actually a massive 192KB instruction cache. That’s absolutely enormous and is 3x larger than the competing Arm designs, and 6x larger than current x86 designs
https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...
Of course since AMD and Intel sell chips directly, holding down die size was directly linked to the amount of profit they could make per wafer. Now that there's more competition, we've seen them do things like radically expand cache sizes.
A necessity. ARM code density is awful, thus a huge L1 is needed to compensate.
This is costly, and ARM's Achilles heel.
The point being, it is a bottleneck and it's possible to do far better. RISC-V has (by far) the best code density among 64bit ISAs.
Apple would have threatened to move to RISC V if ARM allows Qualcomm to continue with Nuvia.