The ECC that is standard with consumer DDR5 is purely on-die, protecting the data at rest but not providing any ECC for the memory bus. It's transparent to the host system. As a result, the CPU and other components do not even have the option of participating in that ECC. It's not a substitute for and does not preclude the use of module-level ECC as in previous generations.

On-die ECC also isn't new with DDR5; it's been used for years on at least some LPDDR4 and LPDDR4x memories (eg. https://www.micron.com/about/blog/2017/february/the-advantag...) and even longer for special-purpose DRAM parts.