If any chip manufacturer can hear me: please, change this metric to transistor per square millimeter. Thanks!
Maybe do it like this: plot nm vs density for "properly" named old nodes and extrapolate further for current nodes.
Completely naive about this level of engineering, but very interested :)
For example (just to chuck some more entropy on the pile) googling "tesla 5nm" finds a bit of an indication they're doing things in that space.
But there's probably also an example of some phone chip that has Cortex A53 cores implemented on two different transistor libraries to hit significantly different performance/power points.
AnD wItH tHe sAmE nUmBeR oF nAnOmEtErS tOo lol
The solution is simple: treat their numbers as brands. A Core i9 is generally better than an i3 of the same generation, but where a Ryzen 5 is compared to that is anyone’s guess (depends on the exact models, generations, etc).
Node sizes have had nothing to do with a characteristic length for quite a while now, that ship has sailed.
For example the scaling factor from from say 5nm to 3nm for transitory is X. But for SRAM, things have been getting progressively worse so it often X/2.
And with caches going up you end up using a process node terrible for sram, but needed for cpu transistors, and it’s a huge waste. You can see why you might use a different process tech for caches, and AMD is clearly going this direction.
Anyhow, TMSC 3nm is just a marketing term. On the physics side, it has about 7-8 key differences to previous 5nm. That’s 6-7 too many things for people to care or remember about.
Intel used to use a part of the transistor when it takes about scale. But then the geometry of the transistor changed! That number no longer has meaning. And transistor geometry changes over time, and you have multiple to choose from on the same process node. Oops.
So… back to marketing terms.
The only people upset with this are benchmark warriors. People in the industry or familiar enough know how to navigate the characteristics of a process and do not need one single neat number. Customers by and large don’t care: business are after the cheapest and best supported, and consumers are mostly price-sensitive except for higher-end brands that don’t communicate at all on this sort of things.
This would not solve any of the industry’s problems.
I think there's problems with that metric too. Not all transistors are created equal. Depending on the switching speed that you want, how much leakage current you can tolerate, etc., I bet you can vastly change how many transistors you can fit in a given area.
https://skywater-pdk.readthedocs.io/en/main/contents/librari...
See how there are six foundry provided cell libraries that make different performance, power and area trade-offs. Even though it’s all 130nm.
There are even more libraries than that too. Like the OSU one that makes even different trade offs.
[1] https://read.nxtbook.com/ieee/spectrum/spectrum_na_august_20...
This won't help in terms of clarity of how good the transistor is. As others mentioned, there are different kinds of transistors and different manufactures would still use their smallest (read not necessarily the fastest/strongest/mostly used) to market their process.
A major reason I think this won't work is that transistor size no-longer limits the density of the chip. Nodes below 20nm have transistor contacts (what connects the silicon to metal), and metal tracks that are much larger than the transistor. The contacts typically limit the pitch between transistors and hence the density. A lot of innovation is now done to shrink those elements rather than work on the transistor physics/materials/size directly.
Layman question from not GP, but wouldn't reducing the "overhead" around transistors increase the transistors-per-area metric and thus be at least somewhat useful?
As you shrink the contacts and the metals their resistance and capacitance exponentially increase. This means that both your power will go up and your speeds will go down. Also the process becomes more prone to manufacturing errors. So shrinking those elements blindly without innovation just to increase the density numbers is not really a good metric of the quality of the process.
transistor switches /( s * mm * Joule) ?
Koomey's law seems to hold strong.
I work in Analog so I'd like a more analog based definition (which also works for digital tbh) based on size or density, trans-conductance(gm), output resistance (ro), and Unity frequency (fT) but that's never going to happen :<
Ideally you'd have some sort of metric that includes power efficiency, performance, and maybe even cost since smallness isn't really a feature in itself unless you're making something space-constrained like a hearing aid. It's hard to condense that down into a single number though.
I don't think this is fair though. Some processes may support finfet, or gaffet, or some neat trick, where, if you switched to the process, but didn't optimize for size, you may be able to double the performance at half the power.
Like you suggest, it's some crazy multidimensional problem space. There's no hope in representing it with one number. And, nobody that's actually designing would care about any of these numbers. In the end, they would only be used by marketing, which is all they're used for now.
Well, you technically can, but it's not starting with a thicker wafer, it's growing a second (or more) layer of dopable silicon on top of the normal doped silicon/transistor gate insulator/wiring/more wiring/even more wiring stack of the chip, then adding another full stack on that new dopable surface. Pretty sure the fabrication infrastructure for that makes conventional, GDP-of-a-small-country photolithography fabs look cheap by comparison, though. Plus you'd be at least squaring (and probably much worse) the already not very good production yield.
Actually, you probably can't; the distance between the sides is practically astronomical compared to the horizontal feature size. I don't remeber the exact actual dimensions, but if you assume a a 1-nm trace is equivalent to a 10-meter road, then a 1-mm wafer thickness would be equivalent a 10'000-km planetary diameter, so you're getting close to the scale of routing a internet cable through the center of the earth. (At least it's not molten, I guess?) And doping generally works by diffusion, not drilling a hole.
I naively assumed you could get an interconnect through, by taking up a large area of silicon. :)