If backside power requires say 10 more imaging steps, then for a given number of imaging machines you can produce fewer wafers per month.
If there is strong demand for the new process (which, since it'll be industry leading I'm sure there will be), you make more money if you can produce more wafers per month but missing a feature.
As demand reduces and more imaging machines get delivered, then it makes sense to add in backside power again.
Intel tried to do too many things at one time with 10nm and it set them behind over half a decade.
I assume there'd also be yield implications, since each step would add risk that something gets screwed up.
Removal of solvents and unused dopants might be more complex depending upon the step in processing.
Does the step require EUV? That laser-pulsed tin isn't free for the asking.
A nanosheet device will have to get thicker for an equal performance to FinFET if they want to keep the number of layers sane.
This is why it's accepted that first generations of multilayer GAA devices will be inferior to FinFETs of equivalent density.
Everybody is of course searching for how to do multiple nanosheets with single imaging step.
20 years old experimental nanosheet designs won't do it in production today. I.E. cutting multiple sheets with RIE is way too coarse, and destructive for modern feature sizes. Depositing sheets into a negative pattern on a sacrificial poly layer brings alignment issues.