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Comment by Jabbles | Hacker News Reader

Standard reminder:

The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the semiconductor chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.

https://en.wikipedia.org/wiki/2_nm_process

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Yeah, it's annoying, but you can see how it happened: the nomenclature was accurate from 10µm to 32nm, and became marketing rather than measurement slowly, not all at once.

The choices are rename everything in the past according to a new objective standard (impractical), make a clean break and use a new objective standard (but what?), or just let 'nm' become some rough and increasingly useless way of indicating die density, where lower is better. So that's what happened.

Up until about 2003 or so, scaling worked near-perfectly, so geometries were essentially the same from generation to generation. This meant that one number, describing minimum feature size, told you what you needed to know. Eventually leakage current became a major issue, so fabs had to do major redesign and change the shapes of the transistors, and different foundries did this differently so that minimum feature length is no longer directly comparable.

You can still compare density: how many transistors or gates in a given area.

> You can still compare density: how many transistors or gates in a given area.

I would say that comparing density comes with its own caveats. E.g. SRAM is denser than logic, so a chip with a lot of cache could skew a density metric. I guess for a true "apples to apples comparison" of processes you'd want to implement the same design on separate nodes with a mixture of SRAM & logic.

Are there any reference designs used for this?

Why is it impractical? I know nothing about CPU architecture.

Clearly we aren't measuring performance with x-nm terminology, but the manufacturing process. Can we not use transistor density per mm^2, or if 3-dimensional, by mm^3?

Looking forward to negative nanometer processes in the future

Yeah I’m also wondering what’s going to happen at that point.

Most likely they'll just switch to picometers, then femtometers, etc, each one yielding 10 generations or so

In a silicon crystal, the minimum distance between atoms is 0.235nm. So, no.

In marketing, anything is possible

Yeah we’ve already entered marketing land when it comes to this years ago.

I think the most realistic guess would probably be a switch to some different nomenclature like G1, G2, G3 etc for generations or literally anything else like product lines (see what happened to nvidias/amds graphics card numbering, etc)

The fact that is is shorthand for "increased speed and reduced power consumption" seems to make it a perfect metric for comparing chips, especially for those of us who have zero interest in learning more than one metric to compare chips (almost everyone).

That's disappointing

I always liked to believe that when two fourth-generation fighters fell in love, they produced an F-35.

Is there a meaningful metric that changes between generations, that could alternatively be used, perhaps by consumers in spite of marketing's desires?

Yes.

The correct figure of merit is transistor density MTr/mm² (millions of transistors per squared millimeter). In reality transistor count is not actually transistor count.

Transistor count/area = 0.6 × NAND2/area + 0.4×[Scan Flip Flops]/area

Weren't "3D chips" a thing? Did that take off/used anywhere. Sounded like a big deal along with the idea of smaller = better.

You're still limited to thermal and cooling capacity if im not mistaken.

Yes it’s used in FLASH now. Look up 3D NAND.

It’s mostly hopeless for compute though because it’s difficult getting rid of the heat.

There's "3D V-cache" now too (cache on top of compute, or something along those lines).

If you are referring to 3D devices like FinFET then they are absolutely a thing and is being used pretty widely. If you are referring to stacking devices in 3D space then the power density becomes too much and it becomes impractical

Transistors are more "3D" now, that's why a 10nm process gives you something like the same density as what a 2D planar transistor with 10nm minimum gate length would. See "FinFET" or "GAA" transistors

If you're talking about stacking entire chips, yes that's also used lots of places.

The challenge there is getting rid of the heat from those chips. If you stack lots of chips it gets really hard to get heat out of the ones in the middle.

Those names are relevant in planar processes (32 nm was last planar prosess for Intel). With FinFets, Gate-All-Around, ribbon fet etc. that makes no sense.

The correct figure of merit is transistor density MTr/mm² (millions of transistors per squared millimeter). In reality transistor count is not actually transistor count.

Transistor count = 0.6 × NAND2/area + 0.4×[Scan Flip Flops]/area

So how many nanometers is the smallest physical feature now?

Varies from fab to fab.

More like varies from marketing department to marketing department.

The dimensions that matter are the pitches of the transistors (i.e. of their gates) and of the first layer of metal interconnections, because these are the dimensions which determine the size of a logical gate or of a memory cell.

For state-of-the-art CMOS processes, these pitches are in the range 30 nm ... 50 nm.

See for example the table "Comparing Intel 4 to Intel 7", at:

https://www.anandtech.com/show/17448/intel-4-process-node-in...

That seems very disingenuous and disappointing!

I hate that that's legal.

Imagine if the food industry could get away with this in their marketing:

"10g Fiber Bars" (fiber bars actually contain only 1g of fiber, "10g fiber" just refers to the fact that it's the 10th generation of fiber bar they've created)

Oh yeah? But my fiber bars are Asbestos Free! (thanks XKCD, I hate whoever figured this out too)

Like household products marketed as "not tested on animals" when all the compounds in the product were already tested on animals a century ago and the overhead for using any novel compounds would mean a vastly higher price (and probably animal testing).

Gypsum water is a thing: https://en.wikipedia.org/wiki/Three_Legs_Cooling_Water I've been given this as a treatment for a cold/flu. I drank it (didn't want to be rude) but couldn't stop thinking about how gypsum used to sometimes be contaminated with asbestos (due to coming from the same mines, I think, long ago).

Why do you care what the minimum gate length is of a process? Do you design standard cell libraries? Transistor density is the only thing you actually care about, and they've continued decreasing the numbers to roughly match what you'd expect from the "nm" number with old planar transistors.

The comparison to a "10g fiber bar" doesn't work, because in the case of semiconductors the "10g fiber bar" is 10 times better than a "1g fiber bar"

TSMC has sometimes started to use eg. N7 instead of 7nm.. but it really doesn't matter.

I don't necessarily care what the minimum gate length is. But I don't like misleading marketing terms that ostensibly give you information about the product, but in reality don't give you any information at all.

If marketing wants to use some metric to convey how good the product is, that's fine, but if the only information being conveyed is the product generation number, they should not be able to masquerade that generation number as a metric. Otherwise it misleads consumers into thinking, i.e. "2nm chips should be able to contain twice as many transistors as 4nm chips!" when that is false.

Actually "2 nm" chips are supposed to have 4 times more transistors than "4 nm" chips, because the area scales like the square of the length.

Because each process generation was supposed to double the transistor density, the names of the processes have been given to correspond approximately with a geometric progression having the ratio sqrt(2): 500 nm, 350 nm, 250 nm, 180 nm, 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, ... , but then the need to round to integer numbers combined with the desire to give distinct names to some process variants that have only small changes in the transistor density (e.g. "6 nm" vs. "7 nm") have lead to deviations from the original progression.

While the transistor density has increased with each process generation, most recent generations have been content with a less than double density, e.g. with a density 1.8 times greater than in the previous generation.

If it doesn't matter why cant they just switch to a density number that translates better than a lookup table and doesn't refer to a measure it has no relationship with anymore?

Would you pay more money for the same product if they switched the nomenclature?

No, but why? Anyway I'd be happier if we stop abusing a measure for nomenclature..

If you're not willing to pay more, it means you don't actually see the change as providing any value.

Because words have meaning, and when a measure /indicator of performance ceases to be a good one we do not simply change the definition of the words we used to us, instead we come up with something new

i.e when Ghz stopped being a useful metric (or sole metric) for CPU we switched to other measurements, we did not redefine what Ghz represented.

i.e when Ghz stopped being a useful metric (or sole metric) for CPU we switched to other measurements, we did not redefine what Ghz represented.

They really did try to muddy the waters back when CPU clock was the only commonplace metric of CPU speed the general consumer would know about though -- as a couple examples, there was the AMD K5 PR200 which was a 133 MHz part but supposedly (according to the AMD marketing team, at least) competitive with a Pentium 200 MHz -- or the AMD Athlon XP 1700+, which does not run at 1.7 GHz as you might think but only about 1.4.

They did stop short of outright calling it GHz, you're right, but clearly the intent was for the consumer to think that a Pentium 4 1700 MHz and an AMD Athlon XP 1700+ were comparable.

Far less annoying and above all far less dangerous than allowing a car company to call their half-baked solution “Auto Pilot”.

I don't think any consumer products get advertised this way? "Now with 2-nm technology inside" is not something anyone cares about. It's not a meaningful benchmark for a chip.

The companies that contract with chip foundries probably know what they're getting. It makes reading industry news a bit more confusing, but for most of us, we're reading it for entertainment, not any practical purpose.

> "10g Fiber Bars" (fiber bars actually contain only 1g of fiber

The supplement industry is good at this. You might see a protein bar with 30g of protein, and find out it's just amino spiking[1]

People in the fitness industry were sending products into labs to have them analyzed and then exposing the companies on YouTube.

[1]:The act of using low grade amino acids (usually L-Taurine and/or L-Glycine) to bump up the overall protein content

Interesting about exposure via YT. Any links to share there?

https://youtu.be/ntSyz018rxw

Similarly as a kid, I was surprised to learn "One-hour Photo" was a brand and didn't necessarily mean your photos would be ready in one hour...

you might be interested why sugar contents is never mentioned as % of daily norm on food packaging in US

It's less that they're marketing deceptively than that the measure they were using stopped making sense. If the ITRS back in the day had known we'd stop using planar transistors they could have named their nodes for the transistor density they achieved but they didn't and so we're stuck with a naming convention that no longer refers to a real physical quantity but we are still getting the density improvements per node that we traditionally have.

Why don't we just switch to that now?

Decades of tradition. And it's not clear exactly what they would switch to, in general transistors double every node but different processes tend to have different design rules so different processes might give you different densities on different designs making the exact reference design a fraught question.

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