Japan, U.S. to launch R&D for 2-nm chip mass production
asia.nikkei.com
asia.nikkei.com
Intel and Toshiba apparently don't see cutting edge device scale as a differentiator and so far haven't invested (enough) in matching TSMC in that arena.
There is very little chance, IMHO, that establishing and funding an independent organization to pursue 2nm will yield the desired results. Providing funding tranched on a results basis to existing firms stands a much better chance, provided that they are permitted to pursue 2 nm fabrication without sharing what they've learned, so they gain the benefit of the effort. If that were the approach, I don't see why the US and Japan need to collaborate at all.
Seems more like narrative-supporting publicity than anything else. Ugh.
On the other hand the US (and Japan, and others) seem to have decided that it is time to hedge their bets.
A lot of the action in semiconductors right now is geostrategic.
States do have an interest in protecting their trading partners, insofar as it's still a good deal. And the poorer the country, the lower the fruit for a hungry invader.
I really want to see a proper head to head of ARM vs x86 with chips at the same fabrication scale - right now part of the reason ARM (and apples new CPU's) are leagues ahead is also just that they are on a different manufacturing process. A modern AMD processor on identical scales might actually be (somewhat) close to the power efficiency of ARM. I'm sure it would still lose but it would be interesting.
Agreed. 2nm-scale manufacturing is contingent on the capabilities available from a complex, interdependent ecosystem of suppliers starting with ASML but continuing to dozens of upstream and downstream sources of essential enabling tech from optics to light sources to resists, etc. Trying to push this from a top-down, government-driven "coordinating" agency will likely fail to accomplish anything meaningful toward the stated goal.
The relevant ecosystem players are already closely collaborating, coordinating or competing. There's no obvious lack of motivation, common ground or communication. And this government effort doesn't have nearly enough money to entirely self-fund things that are both A) likely to make a meaningful difference, and B) aren't already being worked on . Thus, they'll have lots of meetings, then make some bets they can afford funding lower-odds things which aren't likely to pan out (or they'd be the higher-odds things already being bet on by the ecosystem).
But isn't this exactly what China did with Shenzhen and is attempting to do with their semi-conductors as a whole, which is the whole impetus for what the US is doing?
That seems to have changed in the last couple years, though. AMD and Apple seem to have gotten serious.
(I know, Moore's law is about transistor count, and I guess adding more cores technically increases the transistor count. But as a software engineer, I need my chips to get 2x faster every 18 months, or I'll have to start using a profiler or something!)
Problem was that people had certain expectation that a "45nm" process could fit more transistors than "90nm" one. Would be kind of awkward to name it like "22nm++++" and you have no idea roughly how much better it was than the old planar "22nm" process.
One somewhat useful figure you’ll see used is MTr/mm^2 or mega-transistor per square millimeter. That number can change depending on what exactly those transistors are being used for (which cell libraries are used).
IIRC Intel proposed a standard ratio for such measurements a while back.
Density doesn’t make a process better for everything however.
For memory: space, speed, power required, longevity (against time, against temperature / ambient energy).
Computation usually requires some tiny bits of very volatile memory (registers, cache, invisible buffers, etc), but similarly must have tradeoffs for space, speed, power, and longevity.
Radiation Hardened / hostile environment design libraries can also be useful for automotive, heavy industry, military, and space hardened applications. I'm not sure of the details but guess they'd frequently use more space, power, and possibly even active shielding (E.G. additional layers of conductors and/or capacitors sandwiching the logic bits to try to protect them and stabilize local currents).
(At least for FPGA-based satellites. I'm sure there are many varied approaches at play these days.)
I also have reservations on whether the academia can surpass the speed of commercial R&D teams on semiconductor tech. I will believe it when I see it.
ASML's machines have over 4,000 parts in their own supply chains. Many of these are high technology which even ASML does not know how to produce. Many of them come from the U.S. and Europe. The EUV process ASML uses in its most advanced machines was only possible due to investments made by the U.S. government and U.S. companies.
What is happening here is not an attempt by the U.S. and Japanese governments to compete with Taiwan. It's an investment to ensure the next generation of lithographic technology plays out much like the current generation. Meaning the U.S. it's allied governments and many of their respective companies invest enough to acquire leverage over the technology and thus are able to locked China and other countries out of it.
Fabrication is far easier to catch up than bootstrapping. If a country started today, they could subsidize fabrication and within eighteen months they could be making strides to deliver more chips from within. It might literally take a decade or two for a new company to build ASMLs supply chains and replicate one of their machines and that would be 10-20 with no production growth, they would just at that point be getting started.
It is TSMC who integrates the ASML machine into a node. A node being made of dozens of machines performing hundreds of discrete steps with right parameters in the right order. It is TSMC who build fabs with enormously short lead times.
Bootstrapping a whole new lithographic process is not. That is something you would have to invest in for years with essentially nothing to show for it. That is a harder problem from a market standpoint and a political standpoint.
But we're not talking generally about chip fabrication here. We're talking about what is going on with the investments from the U.S. and Japan in next generation chip production. And the bottom line is the investment here is made relatively unrelated to "competing" with Taiwan as a global chip exporter. The most likely thing is that the technology invested here will be used in Taiwan to fabricate chips.
https://www.photonicsonline.com/doc/asml-joins-euv-llc-team-...
It's history as a government/corporate collaboration is the reason ASML can't export EUV machines to China without US permission.
https://www.jstor.org/stable/43294946
tldr just like China today you couldnt just import western electronics to Japan, or gasp own a controlling stake in Japanese companies.
And this was the result:
https://www.washingtonpost.com/archive/opinions/1990/09/30/j...
"JAPAN AND THE BIG SQUEEZE September 30, 1990. HOW DID Japan destroy the American television industry? The secret history of that strategy reveals how Japanese manufacturers and the Japanese government first created an anti-competitive cartel ..."
"Japan's raid on the American market dates back to 1956, when the largest Japanese manufacturers formed the Home Electronic Appliance Market Stabilization Council, an illegal production cartel. The intent of the cartel was to monopolize the domestic market for television receivers, radios and other home electric products and to exclude foreign imports. Once their home market was secure, they would launch a drive against the far richer American market."
Frontline: Coming From Japan [The Fall Of The US Television Industry] (1992) https://www.youtube.com/watch?v=aesJTsZqm6c
That doesn't change that in the mid-70's the Japanese chip manufacturers were failing, and by "pooling together a bunch of also-ran teams together" they actually made better quality chips than the US, not just cheaper ones.
Devs: I'm going to write this in javascript
My question is, does the development of 2-nm happen totally independently of 3-nm? Are they happening concurrently, and 3-nm just got a head start?
Do the advances made during development of 3-nm factor in to the design of 2-nm?
Or is each "N-nm" a somewhat clean slate that brings an entirely new process?
Does each fab invent its own process for N-nm? Or does the "N-nm process" for TSMC look the same as another fabs?
(replies need not say "ackshually, 2-nm is not really 2-nm". we all know this. 90% of the comments so far are about this haha)
At the foundry level, roadmap and research is always ongoing many nodes into the future. The degree of resources provided to a node is of course proportional to how close to becoming a source of revenue it is. Typically different nodes are owned by different development organizations, but they will frequently share development insights with each other. Sometimes the "more researchy" nodes come up with something so great that adoption gets pulled in closer to the current node.
Throughout this process, the foundry is in discussions with OEMs (AMAT, Lam, TEL, ASML, ASM etc), iteratively providing product requirements, and then as the manufacturing cut-in date approaches, a winning vendor/tool is selected for each layer/unit step for the node in question, and the device integration is frozen for high volume manufacturing.
> Does each fab invent its own process for N-nm? Or does the "N-nm process" for TSMC look the same as another fabs?
They all use the same OEMs, and device physics and scaling is the same for everybody, so typically they end up looking pretty similar. However often there is no clear "best" way to solve an integration problem, so you you end up with different solutions depending on the foundry -- and often those solutions are driven more by business considerations and existing supplier relationships than technical merit. In other cases somebody (historically, Intel) comes up with an idea so powerful (FinFET) that everyone else (TSMC) steals it.
The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the semiconductor chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.
I always liked to believe that when two fourth-generation fighters fell in love, they produced an F-35.
Imagine if the food industry could get away with this in their marketing:
"10g Fiber Bars" (fiber bars actually contain only 1g of fiber, "10g fiber" just refers to the fact that it's the 10th generation of fiber bar they've created)
The comparison to a "10g fiber bar" doesn't work, because in the case of semiconductors the "10g fiber bar" is 10 times better than a "1g fiber bar"
TSMC has sometimes started to use eg. N7 instead of 7nm.. but it really doesn't matter.
If marketing wants to use some metric to convey how good the product is, that's fine, but if the only information being conveyed is the product generation number, they should not be able to masquerade that generation number as a metric. Otherwise it misleads consumers into thinking, i.e. "2nm chips should be able to contain twice as many transistors as 4nm chips!" when that is false.
Because each process generation was supposed to double the transistor density, the names of the processes have been given to correspond approximately with a geometric progression having the ratio sqrt(2): 500 nm, 350 nm, 250 nm, 180 nm, 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, ... , but then the need to round to integer numbers combined with the desire to give distinct names to some process variants that have only small changes in the transistor density (e.g. "6 nm" vs. "7 nm") have lead to deviations from the original progression.
While the transistor density has increased with each process generation, most recent generations have been content with a less than double density, e.g. with a density 1.8 times greater than in the previous generation.
i.e when Ghz stopped being a useful metric (or sole metric) for CPU we switched to other measurements, we did not redefine what Ghz represented.
They really did try to muddy the waters back when CPU clock was the only commonplace metric of CPU speed the general consumer would know about though -- as a couple examples, there was the AMD K5 PR200 which was a 133 MHz part but supposedly (according to the AMD marketing team, at least) competitive with a Pentium 200 MHz -- or the AMD Athlon XP 1700+, which does not run at 1.7 GHz as you might think but only about 1.4.
They did stop short of outright calling it GHz, you're right, but clearly the intent was for the consumer to think that a Pentium 4 1700 MHz and an AMD Athlon XP 1700+ were comparable.
The companies that contract with chip foundries probably know what they're getting. It makes reading industry news a bit more confusing, but for most of us, we're reading it for entertainment, not any practical purpose.
The supplement industry is good at this. You might see a protein bar with 30g of protein, and find out it's just amino spiking[1]
People in the fitness industry were sending products into labs to have them analyzed and then exposing the companies on YouTube.
[1]:The act of using low grade amino acids (usually L-Taurine and/or L-Glycine) to bump up the overall protein content
The correct figure of merit is transistor density MTr/mm² (millions of transistors per squared millimeter). In reality transistor count is not actually transistor count.
Transistor count/area = 0.6 × NAND2/area + 0.4×[Scan Flip Flops]/area
It’s mostly hopeless for compute though because it’s difficult getting rid of the heat.
If you're talking about stacking entire chips, yes that's also used lots of places.
The challenge there is getting rid of the heat from those chips. If you stack lots of chips it gets really hard to get heat out of the ones in the middle.
For state-of-the-art CMOS processes, these pitches are in the range 30 nm ... 50 nm.
See for example the table "Comparing Intel 4 to Intel 7", at:
https://www.anandtech.com/show/17448/intel-4-process-node-in...
The choices are rename everything in the past according to a new objective standard (impractical), make a clean break and use a new objective standard (but what?), or just let 'nm' become some rough and increasingly useless way of indicating die density, where lower is better. So that's what happened.
You can still compare density: how many transistors or gates in a given area.
I would say that comparing density comes with its own caveats. E.g. SRAM is denser than logic, so a chip with a lot of cache could skew a density metric. I guess for a true "apples to apples comparison" of processes you'd want to implement the same design on separate nodes with a mixture of SRAM & logic.
Are there any reference designs used for this?
Clearly we aren't measuring performance with x-nm terminology, but the manufacturing process. Can we not use transistor density per mm^2, or if 3-dimensional, by mm^3?
The correct figure of merit is transistor density MTr/mm² (millions of transistors per squared millimeter). In reality transistor count is not actually transistor count.
Transistor count = 0.6 × NAND2/area + 0.4×[Scan Flip Flops]/area
China got the island because no one lives there
US got talents
Taiwan can have freedom
It's not a very densely populated country, with density of 33.6/km².
Compare that to Taiwan at 650/km².
New York City is 778.2/km².
On top of that, America's politics are horribly toxic and the country is about to become a Christian fascist dictatorship that resembles the Handmaid's Tale. Why would they want to move there?
https://www.nytimes.com/1982/02/28/business/japan-s-big-lead...
Tech is there not scale.