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A more realistic direction is up. Or, 3d integration. When the manufacturing gets mature, this gives a large immediate boost, because in two chips of size n/2 that are bonded together, the maximum distance between any two circuit elements is smaller than in a single chip of size n. After that, it will allow scaling by increasing layers.

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Agreed, but we should note that the fundamental problem is not transistor density or quantum physics, but heat dissipation. Going 3D makes smaller process nodes less important, but efficiently removing heat from a die stack is a real challenge. Sandwich a 130W TDP processor die between two other similar die and the heat dissipated per cm^2 is tremendous.

IANAEE but is there some way to integrate peltier junctions into a 3D microchip design so that the heat all gets funneled out of the CPU in a regulated and controlled manner?

Not my area of expertise, but I believe most research today is on microfluidics, introducing microchannels into 3D interconnect layers alongside the TSVs to cool the device. For example, http://deepaksekar.weebly.com/uploads/1/9/8/6/1986457/3d_mic...

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