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Comment by amilios | Hacker News Reader

Something I always wondered: the Gamecube had an IBM PowerPC processor with a RISC instruction set. ARM is also a RISC instruction set. Is there some performance boost in running Dolphin on ARM-powered hardware, or is it more or less the same as running it on an x86-based chip? My sense is that RISC -> RISC potentially would be more straightforward?

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They elaborated on this a little more in their post about Dolphin on the M1: https://dolphin-emu.org/blog/2021/05/24/temptation-of-the-ap...

> AArch64 does have its advantages, though. Namely, the processors have 31 registers, compared to the 16 available in x86-64 processors. The PowerPC processor we are emulating has 32 registers, and while it is rare for all of them to be used within a single code block, more registers is always nice to have. Another difference is that AArch64 and PowerPC have 3 operand instructions while x86-64 only has two.

    PPC:     A = B + C  
    AArch64: A = B + C  
    x86-64:  A = B, A = A + C

> As you can see, it makes emulating some instructions much cleaner and easier than on our x86-64 JIT.

So yes, it is certainly more straightforward: the JIT can do something closer to a one-to-one translation without having to spill registers as often. But they don't go into detail about how much of a performance benefit that is; I'd imagine a small boost but not something too drastic.

To my understanding the only way you'd see a performance benefit is if Dolphin were running on a machine with a PowerPC or some other POWER-based CPU, since most or all instructions would no longer need to be emulated, making it closer to virtualization.

It'd be interesting to see old G3, G4, and G5-based Macs repurposed as deluxe GameCube and Wii emulators. Potentially Wii U too, but I'd imagine that would be restricted to tail-end models of multi-CPU G5 towers with the best GPUs those machines can handle.

Correct, plus big-endian, plus any emulation for opcodes not supported by the host CPU (like paired singles, or mcrxr on G5 and up), plus any cacheline size impedance mismatches. It should be possible to run such code in the standard PowerPC problem state but it wouldn't be trivial.

The way I remember is that RISC is just a class of computer design. The different architectures aren't necessarily close to each other (only that they have a reduced instruction set compared to other systems), so I can't imagine that this helps.

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