Hacker News Reader

Comment by derekdahmer | Hacker News Reader

What’s the technical limitation in increasing the number of voltage levels? Why not say 64 or 128 levels?

The more complicated the modulation is, the more processing power is required. DSL modems use very complex modulation to push their data across the wire and burn a few Watts doing so (there's also a fairly powerful line driver, but that's not the main power consumer, the DSP/modem itself is).

Of course, SNR is another big one. You have to actually be able to distinguish the voltage levels within a symbol period from each other.

Another thing: PCIe is meant to be low-latency, which just rules out a lot of the modulation and error-correction techniques that are traditionally used to enhance channel utilization, like having multiple levels of FEC and then interleaving FEC symbols temporally. That's done basically always where latency allows, e.g. in storage media, digital TV and so on.

Differentiating between black and white is easy. Distinguishing between fifty shades of grey is difficult.

Excellent analogy.

He already said it. Noise.

With 2 levels you have low and high. I have no idea if PCIe is 1.8V but let’s be really gracious here and pretend it’s 5V.

Ok; so at 5V and 4 levels you have Sig Al’s between 0V, 1.25V, 2.50V, and 3.75V. And are encoding 2 bits per clock.

At 64 levels you have a signal every 0.078125V. It’s going to be really hard to capture that signal at a moment in time and at these speeds be certain if it’s definitely A or B.

At some point you get into modems (modulation, demodulation) but the add much more cost, latency, and complexity.

So before getting into radio and analog tech, here is a simple way to double the bandwidth for little cost. A driver only needs 0,1,2,3 levels and a receiver can make fairly confident guesses quickly.

I’m pretty sure PCIe isn’t 5V. Probably more like 1.8V, so already starting with a much smaller range.

Riding on the coat-tails of the noise problem is power. PAM-4 is an easy win because 2-level signalling is "over-margined" (which is why you don't need error correction with 2 levels, but you start to rely on it more and more as the # of levels goes up).

The "easiest" way to get around noise problems is to put more signal in, but power consumption increases with the square of voltage -- so it's extremely costly to overcome noise with more signal. However, noise is a fundamental limit; there's a set of tricks you can maybe do to improve it but for example, kT/q (thermal voltage of noise at roughly room temp) is about 25mV and that plays a role in a lot of device physics.

Thus most signals engineers would steer away from higher-order PAM and go to QAM, where they use phase to encode one dimension of data, and voltage to encode the other. This gets you out of a one-dimensional line of voltages and into a two-dimensional matrix of voltage vs. time to represent information.

This helps fight against that square-law term for power, but it comes at the expense of more precise timing sources. Time also has noise mechanisms, that are typically only overcome at the expense of -- you guessed it -- power.

At the end of the day, probably the most fundamental limit all computation will run into is power -- both how much you can afford to put in, and more importantly, the limit of what you can pull out reliably and efficiently. I'd be curious to see the plot of PCI-express energy-per-bit over its generations...I suspect it improves over time, but not improving as fast as bandwidth is going up, which means in net each link should run hotter.

> I’m pretty sure PCIe isn’t 5V. Probably more like 1.8V, so already starting with a much smaller range.

I'm fairly sure the most modern PCIe standards are all the way down to 1.2V. Prior to 1.2V it was 1.5V, 1.8V, 2.5V, and back in the days of the original spec it was 3.3V. I can't remember exactly what versions speced what voltages.

Modern PCIe uses a complicated transceiver design that does pre-emphasis/de-emphasis on the signal. The actual signal swing is differential, and on the order of +/-200mV (with a relatively low voltage common mode, on the order of 300mV) after all the attenuation.

What the actual digital IO voltage that the chip that does PCIe driver is driven from is almost unrelated.

More like +-350mV

Noise is a big one. The more levels you have, the more likely it is noise is going to turn a 0 to a 1 or a 1 to a 2, for example. It also requires more complicated switching transistors, because you can't rely on things being simply on or off, but rather have to generate a number of intermediary voltages.

Differential signaling is one way to combat a lot of noise, which I do believe is used in the PCI spec already.

PCI[1] didn't use differential signalling, however it did use reflected-wave switching[2]. PCI express[3] does use differential signalling, as does a lot of other higher-speed busses like USB, SATA, or MIPI CSI-2/3[4].

[1]: https://en.wikipedia.org/wiki/Peripheral_Component_Interconn...

[2]: https://en.wikipedia.org/wiki/Reflected-wave_switching

[3]: https://en.wikipedia.org/wiki/PCI_Express#Lane

[4]: https://en.wikipedia.org/wiki/Camera_Serial_Interface

It doesn't eliminate all noise. You can play these games, but can never violate Shannon's. We hit Baud rates where channel loss was high enough that the SNR needed to be cut into to get more throughput. This cut the SNR so much that FEC was needed to maintain an acceptable error rate. PCIe lags IEEE 802.3 with these kinds of things. I'd call it bog standard but it's still bleeding edge.

The other answers miss the point.

A flip flop can be calibrated to the difference potentials of thr input. You have zero and one as a result, no processing required. Single bit, single voltage. Simple.

Think about what it means to map a single voltage input to multiple bits. What device would do it? A complex ADC? Think of the overhead that would introduce.

Am I incorrect in thinking that you can smartly place some resistors to turn your, say, 4 level voltage difference into two inputs with some resistors? It's been a long time since I took electronics but surely that's not a complex problem requiring "complex ADC" right?

Though I could imagine at one point you're just looking at larger buses and having to deal with those consequences

Unless I misunderstood you, what you're describing is essentially a flash ADC[1]. It's very fast, and not that complex for a low number of bits. But it scales poorly to higher bit depths.

I wouldn't be surprised if that's what they'll be using, though I'm not an expert either so might be better options out there.

[1]: https://en.wikipedia.org/wiki/Flash_ADC

Needs comparators though, not only resistors. It's not easy to make them super fast.

I don't know enough of chip design to say more, I just know it's been done[1].

I know interleaving is another approach[2] for reaching high sample rates, though it introduces latency.

What other approaches are there for low-precision multi-Gs/s ADCs?

[1]: https://www.analog.com/media/en/technical-documentation/data...

[2]: https://www.analog.com/en/technical-articles/a-12-b-10-gss-i...

ADCs are slow. With four levels they're probably using comparators.

Reply on news.ycombinator.com