Since they will be pushing the limits of the SNR, they also build in forward error correction to keep the error rate under control.
I'm amazed at the progress of terabit Ethernet, soon 1.6Tbit/s in one server.
https://en.wikipedia.org/wiki/Quadrature_amplitude_modulatio...
EDIT: nvm, you can't get extra bandwidth by breaking spectral symmetry on a baseband signal because the signal would become complex valued.
[1]: https://en.wikipedia.org/wiki/Peripheral_Component_Interconn...
[2]: https://en.wikipedia.org/wiki/Reflected-wave_switching
Of course, SNR is another big one. You have to actually be able to distinguish the voltage levels within a symbol period from each other.
Another thing: PCIe is meant to be low-latency, which just rules out a lot of the modulation and error-correction techniques that are traditionally used to enhance channel utilization, like having multiple levels of FEC and then interleaving FEC symbols temporally. That's done basically always where latency allows, e.g. in storage media, digital TV and so on.
With 2 levels you have low and high. I have no idea if PCIe is 1.8V but let’s be really gracious here and pretend it’s 5V.
Ok; so at 5V and 4 levels you have Sig Al’s between 0V, 1.25V, 2.50V, and 3.75V. And are encoding 2 bits per clock.
At 64 levels you have a signal every 0.078125V. It’s going to be really hard to capture that signal at a moment in time and at these speeds be certain if it’s definitely A or B.
At some point you get into modems (modulation, demodulation) but the add much more cost, latency, and complexity.
So before getting into radio and analog tech, here is a simple way to double the bandwidth for little cost. A driver only needs 0,1,2,3 levels and a receiver can make fairly confident guesses quickly.
I’m pretty sure PCIe isn’t 5V. Probably more like 1.8V, so already starting with a much smaller range.
The "easiest" way to get around noise problems is to put more signal in, but power consumption increases with the square of voltage -- so it's extremely costly to overcome noise with more signal. However, noise is a fundamental limit; there's a set of tricks you can maybe do to improve it but for example, kT/q (thermal voltage of noise at roughly room temp) is about 25mV and that plays a role in a lot of device physics.
Thus most signals engineers would steer away from higher-order PAM and go to QAM, where they use phase to encode one dimension of data, and voltage to encode the other. This gets you out of a one-dimensional line of voltages and into a two-dimensional matrix of voltage vs. time to represent information.
This helps fight against that square-law term for power, but it comes at the expense of more precise timing sources. Time also has noise mechanisms, that are typically only overcome at the expense of -- you guessed it -- power.
At the end of the day, probably the most fundamental limit all computation will run into is power -- both how much you can afford to put in, and more importantly, the limit of what you can pull out reliably and efficiently. I'd be curious to see the plot of PCI-express energy-per-bit over its generations...I suspect it improves over time, but not improving as fast as bandwidth is going up, which means in net each link should run hotter.
I'm fairly sure the most modern PCIe standards are all the way down to 1.2V. Prior to 1.2V it was 1.5V, 1.8V, 2.5V, and back in the days of the original spec it was 3.3V. I can't remember exactly what versions speced what voltages.
What the actual digital IO voltage that the chip that does PCIe driver is driven from is almost unrelated.
A flip flop can be calibrated to the difference potentials of thr input. You have zero and one as a result, no processing required. Single bit, single voltage. Simple.
Think about what it means to map a single voltage input to multiple bits. What device would do it? A complex ADC? Think of the overhead that would introduce.
Though I could imagine at one point you're just looking at larger buses and having to deal with those consequences
I wouldn't be surprised if that's what they'll be using, though I'm not an expert either so might be better options out there.
I know interleaving is another approach[2] for reaching high sample rates, though it introduces latency.
What other approaches are there for low-precision multi-Gs/s ADCs?
[1]: https://www.analog.com/media/en/technical-documentation/data...
[2]: https://www.analog.com/en/technical-articles/a-12-b-10-gss-i...
Remember socket AM4, which added support for PCIe 4.0 with chipset X570? Originally, the idea was that non-X570 boards would also have PCIe 4.0, as it doesn't actually depend on the chipset - just the CPU. Turns out most boards simply weren't capable of handling the additional bandwidth, so it was eventually restricted to boards which were designed for it. And that's at one-eighth the bandwidth of PCIe 7.0!
In practice it's a bunch of point-to-point links, but even then the path across a PCB is pretty brutal in terms of loss. Cables are (surprisingly to me, initially!) better.
Overall though, sending some number of additional bits for error correction is often cheaper than driving the line harder to reduce the bit error rate.
Put differently: we could manage lower noise, but it would either result in a lower bitrate or (much) higher power. Instead, pick a target goodput and design for power and error correction from both sides.
That's because the cables in these application are not single wires but complex micro-coaxial assemblies. (The industry best is 3M Twin Axial.) And that will have much more shielding than an inherently unshielded PCB trace. With an appropriate price, of course.
Note that on balance I'll take something like an OSFP assembly (https://www.te.com/usa-en/products/connectors/pluggable-conn...) with a fancy jacket that pulls all of the individual twinax cables together, but it's also substantially more expensive than a simple flat tape-wrapped ribbon.
Other places where you'll see coax cables ganged together inside a jacket: high-speed USB cables. For example, here's a type C cable cross-section: https://twitter.com/tubetimeus/status/1125926941469462528
At this point the bits are millimeters long.