(2019)
IMO it's also debatable whether or not it should be really called RISC-V, because RISC-V doesn't have a 16-bit ISA. Instead this seems to use the same ISA, but it limits both data and addresses to 16-bits (while keeping 32-bit instructions).
IMO it's also debatable whether or not it should be really called RISC-V, because RISC-V doesn't have a 16-bit ISA. Instead this seems to use the same ISA, but it limits both data and addresses to 16-bits (while keeping 32-bit instructions).
It is possible to e.g. have 32bit registers but 16bit ALU (and do 32bit operations in steps, hidden from the programmer).
This is how the 68000 worked.
But using the RISC-V instructions means that all kinds of existing tools will work just fine for them as long as their programs keep within the limitations. No need to write their own assemblers and such.
32-bit instructions, 3 registers, 16-bit addresses/data, and no fancy addressing modes (only lh reg, a(reg) and sh reg, a(reg)), sounds absolutely painful to program for. Like a 6502 without the zero page, and half the instruction density.