16-bit RISC-V processor made with carbon nanotubes (2019)

arstechnica.com

56 points·signa11··7 comments

(2019)

IMO it's also debatable whether or not it should be really called RISC-V, because RISC-V doesn't have a 16-bit ISA. Instead this seems to use the same ISA, but it limits both data and addresses to 16-bits (while keeping 32-bit instructions).

Also, saying it's made with nanotubes kind of implies that nanotubes was used as transistors. Instead, "nanotubes" seems to be used as a substrate, and the transistors are formed using traditional oxide doping.

Thanks, that was my immediate question on reading the title - I didn't think RISC-V had a 16-bit variant.

It doesn't.

It is possible to e.g. have 32bit registers but 16bit ALU (and do 32bit operations in steps, hidden from the programmer).

This is how the 68000 worked.

And the Z80 had a 4 bit ALU. Note that the 68000 actually had three 16 bit ALUs and could crunch 48 bits per cycle, depending on what operations you were doing since one was a full ALU while the other two more simple adders/subtractors.

It also only implements 3 registers, not 16 (RV32E) or 32 (RV32I), though it might count as 4 since register 0 is hardwired to a 0 value.

But using the RISC-V instructions means that all kinds of existing tools will work just fine for them as long as their programs keep within the limitations. No need to write their own assemblers and such.

Interesting. I didn't know about the 3 registers aspect, although I haven't read the paper since it came out a few years back.

32-bit instructions, 3 registers, 16-bit addresses/data, and no fancy addressing modes (only lh reg, a(reg) and sh reg, a(reg)), sounds absolutely painful to program for. Like a 6502 without the zero page, and half the instruction density.

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