You could do a lot more than that, as there are multiple transistors for each gate (assuming static CMOS).

My company uses FPGAs to for verification during development (because it takes months to get silicon back after tapeout, and it costs millions of dollars even if you only want one single test chip). We make chips that are much more complex than a P3. Friends of mine at other microprocessor companies have told me that they have a similar process, though some of them at larger companies use their own custom hardware for accelerated simulation, since you can't fit anything like a POWER7 or even a core i3 on a commercially available FPGA.