My company uses FPGAs to for verification during development (because it takes months to get silicon back after tapeout, and it costs millions of dollars even if you only want one single test chip). We make chips that are much more complex than a P3. Friends of mine at other microprocessor companies have told me that they have a similar process, though some of them at larger companies use their own custom hardware for accelerated simulation, since you can't fit anything like a POWER7 or even a core i3 on a commercially available FPGA.
The standard wafer they use is around 30 cm, right?
However, the process of implementing circuits in an FPGA isn't that efficient (processors can do a lot of tricks to get better than 2 transistors/gate. They can also do other tricks to do calculations with just transistors instead of gates and FPGA's can't). However given the 4x overhead, I would say, yes, theoretically an Intel engineer with a full spec and some really good VHDL (the programming language of FPGAs) skills could implement a P3 on this.
So when they say "20 million gates", they don't actually mean that any 20M-gate circuit can be built. It depends on what you're doing; some things (e.g. big logic functions) work better in FPGA logic than others (e.g. complicated wiring and bus architectures).