You also have the wrong market segment. This was supposed to be a 25w chip with crazy high i/o. Dual 10Gbit, plenty of pcie & sata... back in 2006... at low power, all integrated... this chip was supposed to be a dara pushing monster.
Maybe they could have scaled down but the intent was obviously different, to deliver performant extremely well integrared embedded & bigger cpus.
Most of that stuff was a result of their very impressive integrated northbridge, but they never publicly demonstrated any CPU that could actually drive all that bandwidth.
Supposedly they had plans to eventually ship a 16 core processor that would really use all of the I/O bandwidth, but they never manufactured anything more than a 7w, dual core part. The Amiga X1000 only featured a single 1 GigE port.
So it’s not like they sold when they had a revolutionary monster ready to dominate the market sitting in warehouses. They had long-term plans, but they may have been starting to doubt the feasibility of executing them, or being relevant by the time they’d scaled the architecture up to sixteen cores, by the time Apple came along.
> The device also integrates a flexible I/O subsystem that supports eight PCI Express controllers, two 10-Gigabit Ethernet controllers and four Gigabit Ethernet controllers that share 24 configurable SERDES lanes.
It's interesting that you highlight the cpu as such a limiting factor:
> they never publicly demonstrated any CPU that could actually drive all that bandwidth.
Agreed that the plans to scale up cores were very interesting & promising. But the other ultra-notable features of this ultra-integrated badass SoC monster (the one that shipped) was that it had a colossal crossbar powered DMA engine.
In many applications the cpu could serve as control plane, & the rest of the chip could act like a data-plane, shipping data around. The northbridge can happily pipe gobs of ethernet over to your SATA system, semi-autonomously.
At the time that usually took special carefully tuned code to pull off, I imagine. I like to think today we'd be able to use this DMA engine far more readily- io_uring for async io, all manners of dma-buf linux capabilities for managing device-side memory, plenty of dma engines & offloads in various kernel drivers. Direct device to device communication has continued to be underscores as a huge way to u leash computing, and wow, PA Semi dedicated gobs of die-space to the task way back then.
Such a huge huge pity such a promising new competitor just vanished.
> They had long-term plans, but they may have been starting to doubt the feasibility of executing them,
They indeed ran hotter than expected & core performance was not nearly what was hoped for. According to various LKML posts of people who had dev boxes. Still, so impressed. Tons of brilliant innovation. A little more runway to get off the ground before being torn apart & swallowed by a titan would have been great.
[1] http://vita.mil-embedded.com/news/p-processor-ever-designed/
Do you mean specifically that Ryzen was the first CPU to offer that kind of IO flexibility? Because Intel desktop chipsets were doing that kind of thing long before Ryzen hit the scene. Here's are chipsets for Haswell and Skylake:
Haswell: https://images.anandtech.com/doci/7963/FlexIO.png
Skylake: https://images.anandtech.com/doci/9582/122%20-%20HSIO%20H.jp...