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Comment by beached_whale | Hacker News Reader

If only intel wasnt dropping support for it on a lot of cpus

Well, if it means more cores, it's almost certainly worth it, in the grand scheme of things.

I'm using this comment as jumping point.

What's cost/opportunity to optimizing for a specific platform/instruction set ? At what point is it worth doing, when isn't it worth doing ? AVX-512 strikes as something... "ephemeral".

Well I mean this article is demoing a 28% improvement (if I did my math right) for json parsing.

Sure AVX-512 is only applicable to specific workloads, and even many of those workloads the cost/opportunity of optimizing for AVX-512 might not be worth it. But there clearly ARE usecases that would benefit, and it might be worth it for more consumer applications to optimize for AVX-512 - but only if it can be used.

The way I see it is that the benefit of optimizing for AVX-512 is far higher if it becomes normal for consumer CPUs to have it. A 28% improvement is pretty decent, but it's only worth implementing if enough people can utilize it.

For many maybe not, but when writing the foundations of software it is good to start fast. There are libraries that abstract various simd architectures now too. Simdjson has their own and there are ones lile KUMI

writing code for SIMD can get you absolutely massive performance improvements. Whether it's worth the added complexity depends on the situation. If your data is already arranged in a cache friendly way (SoA), it shouldn't be incredibly difficult to use SIMD intrinsics to optimize. I'd first take a look at what the compiler is already generating for you to see if manual intervention is worth it.

Intel is not dropping support for it on a lot of CPUs.

The only thing they've done is disable it in the hybrid Alder Lake cores, presumably because the E-cores couldn't support it (while the P-cores could), and they didn't want to deal with the headaches of ISA extensions being supported only on some cores in the system.

> The only thing they've done is disable it in the hybrid Alder Lake cores

That is incorrect. You can buy Alder Lake CPUs that only have one type of core (the i3 series only has P-cores, for example), and those do not support AVX-512 either. They're not "hybrid" in any way.

Some of their motherboard partners initially allowed you to access AVX-512, but Intel has put a stop to this and the feature is disabled on all Alder Lake CPU SKUs, period.

Newer Alder Lake chips have AVX-512 fused off in silicon, if the firmware blob disabling it isn’t enough: https://www.tomshardware.com/news/intel-nukes-alder-lake-avx...

> Intel is not dropping support for it on a lot of CPUs.

That seems like a pretty questionable statement. Intel might keep AVX-512 around for Xeon, but it seems extremely dead on the consumer market. If Intel decides to bring it back for the next generation, that would be strange and very poor planning.

In consumer market, Intel supported AVX-512 only on -X, HEDT processors. There is a rumor that either Adler Lake-X is coming out or it will be folded into Xeon -W workstation line. It will support AVX-512.

I’m fairly sure the bog-standard consumer Rocket Lake processors had AVX-512.

It seems likely that the reason is that some intel customers are willing to pai a significant premium for the feature and intel doesn't want it to be available for cheap

If what they’ve done with ECC memory is any indication, this sort of market segmentation would only slow down or even kill adoption of AVX-512 in the consumer sphere. Welp, at least there’s no reliability issue here, so Torvalds is unlikely to get angry anytime soon.

Probably intel doesn't care about AVX-512 in the consumer sphere.

> Intel is not dropping support for it on a lot of CPUs.

There are 0 current generation consumer CPUs of neither Intel nor AMD that have it

> The only thing they've done is disable it in the hybrid Alder Lake cores

Which happen to be all the current generation Intel CPUs

Ah, headlines foiled me. I read disabled in Alder lake all together.

It is disabled in all consumer Alder lake (and I don't remember if there will be Xeon of that gen with P-core only -- IIRC Intel stop the AVX512 validation late on those cores, but it was still before it was formally finished, so probably not). At one point it worked with some Bios on P-core only chips or if you disabled E-core on hybrid ones, but with up-to-date Intel microcode it does not work anymore.

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