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This is cool but it seems like it occupies an unusual place in tradeoff space. Most of the time SPSC queues would benefit from having the start and end pointers in separate pages, or even having cached copies of the start and end pointers in even more separate pages to avoid atomics[0].

[0]: https://rigtorp.se/ringbuffer/

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But then those accesses have to be protected by a lock in order to enforce invariants between "start" and "end". The whole point of representing both with a single atomic value is that this makes it trivial to preserve those required invariants.

Because the queue grows only in one direction and it is consumed in the other direction, reading a stale value from the other side is still safe, so two-word atomicity is not needed.

In fact the other side value is normally cached in a local memory location so to amortize the cost of roundtrips over multiple reads and writes.

Only for SPSC. You need H/T consistency in other cases for full/empty checks.

Cmon AMD/Intel, give us hardware queues already :)

separate cache lines not pages :)

You are correct, of course

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